kopia lustrzana https://github.com/espressif/esp-idf
366 wiersze
12 KiB
C
366 wiersze
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The HAL layer for I2S (common part)
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "hal/i2s_hal.h"
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/**
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* @brief Calculate the closest sample rate clock configuration.
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* clock relationship:
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* Fmclk = bck_div*fbck = fsclk/(mclk_div+b/a)
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*
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* @param clk_cfg I2S clock configuration(input)
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* @param cal Point to `i2s_ll_mclk_div_t` structure(output).
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*/
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static void i2s_hal_mclk_div_decimal_cal(i2s_hal_clock_cfg_t *clk_cfg, i2s_ll_mclk_div_t *cal)
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{
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int ma = 0;
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int mb = 0;
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cal->mclk_div = clk_cfg->mclk_div;
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cal->a = 1;
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cal->b = 0;
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/* If sclk = 0 means APLL clock applied, mclk_div should set to 1 */
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if (!clk_cfg->sclk) {
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cal->mclk_div = 1;
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return;
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}
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uint32_t freq_diff = clk_cfg->sclk - clk_cfg->mclk * cal->mclk_div;
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uint32_t min = ~0;
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for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
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for (int b = 1; b < a; b++) {
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ma = freq_diff * a;
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mb = clk_cfg->mclk * b;
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if (ma == mb) {
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cal->a = a;
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cal->b = b;
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return;
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}
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if (abs((mb - ma)) < min) {
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cal->a = a;
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cal->b = b;
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min = abs(mb - ma);
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}
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}
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}
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}
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void i2s_hal_set_clock_src(i2s_hal_context_t *hal, i2s_clock_src_t sel)
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{
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i2s_ll_tx_clk_set_src(hal->dev, sel);
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i2s_ll_rx_clk_set_src(hal->dev, sel);
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}
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void i2s_hal_tx_clock_config(i2s_hal_context_t *hal, i2s_hal_clock_cfg_t *clk_cfg)
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{
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i2s_ll_mclk_div_t mclk_set;
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i2s_hal_mclk_div_decimal_cal(clk_cfg, &mclk_set);
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i2s_ll_tx_set_clk(hal->dev, &mclk_set);
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i2s_ll_tx_set_bck_div_num(hal->dev, clk_cfg->bclk_div);
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}
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void i2s_hal_rx_clock_config(i2s_hal_context_t *hal, i2s_hal_clock_cfg_t *clk_cfg)
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{
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i2s_ll_mclk_div_t mclk_set;
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i2s_hal_mclk_div_decimal_cal(clk_cfg, &mclk_set);
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i2s_ll_rx_set_clk(hal->dev, &mclk_set);
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i2s_ll_rx_set_bck_div_num(hal->dev, clk_cfg->bclk_div);
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}
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void i2s_hal_enable_master_fd_mode(i2s_hal_context_t *hal)
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{
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i2s_ll_tx_set_slave_mod(hal->dev, false); //TX master
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i2s_ll_rx_set_slave_mod(hal->dev, true); //RX Slave
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}
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void i2s_hal_enable_slave_fd_mode(i2s_hal_context_t *hal)
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{
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i2s_ll_tx_set_slave_mod(hal->dev, true); //TX Slave
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i2s_ll_rx_set_slave_mod(hal->dev, true); //RX Slave
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}
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void i2s_hal_init(i2s_hal_context_t *hal, int i2s_num)
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{
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/* Get hardware instance */
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hal->dev = I2S_LL_GET_HW(i2s_num);
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}
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#if SOC_I2S_SUPPORTS_PDM_TX
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void i2s_hal_tx_set_pdm_mode_default(i2s_hal_context_t *hal, uint32_t sample_rate)
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{
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/* enable pdm tx mode */
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i2s_ll_tx_enable_pdm(hal->dev, true);
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_tx_enable_clock(hal->dev);
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i2s_ll_tx_clk_set_src(hal->dev, I2S_CLK_D2CLK); // Set I2S_CLK_D2CLK as default
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i2s_ll_mclk_use_tx_clk(hal->dev);
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/* Still need to enable the first 2 TDM channel mask to get the correct number of frame */
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i2s_ll_tx_set_active_chan_mask(hal->dev, I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1);
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#else
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i2s_ll_tx_force_enable_fifo_mod(hal->dev, true);
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#endif
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/* set pdm tx default presacle */
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i2s_ll_tx_set_pdm_prescale(hal->dev, 0);
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/* set pdm tx default sacle of high pass filter */
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i2s_ll_tx_set_pdm_hp_scale(hal->dev, I2S_PDM_SIG_SCALING_MUL_1);
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/* set pdm tx default sacle of low pass filter */
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i2s_ll_tx_set_pdm_lp_scale(hal->dev, I2S_PDM_SIG_SCALING_MUL_1);
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/* set pdm tx default sacle of sinc filter */
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i2s_ll_tx_set_pdm_sinc_scale(hal->dev, I2S_PDM_SIG_SCALING_MUL_1);
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/* set pdm tx default sacle of sigma-delta filter */
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i2s_ll_tx_set_pdm_sd_scale(hal->dev, I2S_PDM_SIG_SCALING_MUL_1);
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/* set pdm tx sample rate */
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i2s_ll_tx_set_pdm_fpfs(hal->dev, 960, sample_rate / 100);
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#if SOC_I2S_SUPPORTS_PDM_CODEC
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/* enable pdm high pass filter */
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i2s_ll_tx_enable_pdm_hp_filter(hal->dev, true);
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/* set pdm tx high pass filter parameters */
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i2s_ll_tx_set_pdm_hp_filter_param0(hal->dev, 6);
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i2s_ll_tx_set_pdm_hp_filter_param5(hal->dev, 7);
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/* enable pdm sigma-delta codec */
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i2s_ll_tx_enable_pdm_sd_codec(hal->dev, true);
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/* set pdm tx sigma-delta codec dither */
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i2s_ll_tx_set_pdm_sd_dither(hal->dev, 0);
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i2s_ll_tx_set_pdm_sd_dither2(hal->dev, 0);
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#endif // SOC_I2S_SUPPORTS_PDM_CODEC
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}
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#endif // SOC_I2S_SUPPORTS_PDM_TX
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#if SOC_I2S_SUPPORTS_PDM_RX
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void i2s_hal_rx_set_pdm_mode_default(i2s_hal_context_t *hal)
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{
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/* enable pdm rx mode */
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i2s_ll_rx_enable_pdm(hal->dev, true);
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/* set pdm rx downsample number */
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i2s_ll_rx_set_pdm_dsr(hal->dev, I2S_PDM_DSR_8S);
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#if !SOC_I2S_SUPPORTS_TDM
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i2s_ll_rx_force_enable_fifo_mod(hal->dev, true);
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#endif
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_rx_enable_clock(hal->dev);
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i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_D2CLK); // Set I2S_CLK_D2CLK as default
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i2s_ll_mclk_use_rx_clk(hal->dev);
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/* Still need to enable the first 2 TDM channel mask to get the correct number of frame */
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i2s_ll_rx_set_active_chan_mask(hal->dev, I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1);
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#else
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i2s_ll_rx_force_enable_fifo_mod(hal->dev, true);
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#endif
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}
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#endif // SOC_I2S_SUPPORTS_PDM_RX
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void i2s_hal_tx_set_common_mode(i2s_hal_context_t *hal, const i2s_hal_config_t *hal_cfg)
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{
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/* Disable PDM tx mode and enable TDM mode (if support) */
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i2s_ll_tx_enable_pdm(hal->dev, false);
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_tx_enable_clock(hal->dev);
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i2s_ll_tx_clk_set_src(hal->dev, I2S_CLK_D2CLK); // Set I2S_CLK_D2CLK as default
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i2s_ll_mclk_use_tx_clk(hal->dev);
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i2s_ll_tx_set_active_chan_mask(hal->dev, hal_cfg->chan_mask);
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i2s_ll_tx_enable_left_align(hal->dev, hal_cfg->left_align);
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i2s_ll_tx_enable_big_endian(hal->dev, hal_cfg->big_edin);
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i2s_ll_tx_set_bit_order(hal->dev, hal_cfg->bit_order_msb);
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i2s_ll_tx_set_skip_mask(hal->dev, hal_cfg->skip_msk);
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#else
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i2s_ll_tx_enable_msb_right(hal->dev, false);
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i2s_ll_tx_enable_right_first(hal->dev, false);
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i2s_ll_tx_force_enable_fifo_mod(hal->dev, true);
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#endif
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}
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void i2s_hal_rx_set_common_mode(i2s_hal_context_t *hal, const i2s_hal_config_t *hal_cfg)
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{
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/* Disable PDM rx mode and enable TDM rx mode (if support)*/
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i2s_ll_rx_enable_pdm(hal->dev, false);
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_rx_enable_clock(hal->dev);
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i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_D2CLK); // Set I2S_CLK_D2CLK as default
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i2s_ll_mclk_use_rx_clk(hal->dev);
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i2s_ll_rx_set_active_chan_mask(hal->dev, hal_cfg->chan_mask);
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i2s_ll_rx_enable_left_align(hal->dev, hal_cfg->left_align);
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i2s_ll_rx_enable_big_endian(hal->dev, hal_cfg->big_edin);
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i2s_ll_rx_set_bit_order(hal->dev, hal_cfg->bit_order_msb);
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#else
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i2s_ll_rx_enable_msb_right(hal->dev, false);
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i2s_ll_rx_enable_right_first(hal->dev, false);
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i2s_ll_rx_force_enable_fifo_mod(hal->dev, true);
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#endif
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}
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static uint32_t i2s_hal_get_ws_bit(i2s_comm_format_t fmt, uint32_t chan_num, uint32_t chan_bits)
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{
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switch (fmt) {
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case I2S_COMM_FORMAT_STAND_MSB:
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return chan_num * chan_bits / 2;
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case I2S_COMM_FORMAT_STAND_PCM_SHORT:
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return 1;
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case I2S_COMM_FORMAT_STAND_PCM_LONG:
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return chan_bits;
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default: //I2S_COMM_FORMAT_STAND_I2S
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return chan_num * chan_bits / 2;
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}
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}
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void i2s_hal_tx_set_channel_style(i2s_hal_context_t *hal, const i2s_hal_config_t *hal_cfg)
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{
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uint32_t chan_num = 2;
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uint32_t chan_bits = hal_cfg->chan_bits;
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uint32_t data_bits = hal_cfg->sample_bits;
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bool is_mono = (hal_cfg->chan_fmt == I2S_CHANNEL_FMT_ONLY_RIGHT) ||
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(hal_cfg->chan_fmt == I2S_CHANNEL_FMT_ONLY_LEFT);
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/* Set channel number and valid data bits */
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#if SOC_I2S_SUPPORTS_TDM
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chan_num = hal_cfg->total_chan;
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i2s_ll_tx_set_chan_num(hal->dev, chan_num);
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#endif
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i2s_ll_tx_set_sample_bit(hal->dev, chan_bits, data_bits);
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i2s_ll_tx_enable_mono_mode(hal->dev, is_mono);
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/* Set communication format */
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bool shift_en = hal_cfg->comm_fmt == I2S_COMM_FORMAT_STAND_I2S ? true : false;
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uint32_t ws_width = i2s_hal_get_ws_bit(hal_cfg->comm_fmt, chan_num, chan_bits);
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i2s_ll_tx_enable_msb_shift(hal->dev, shift_en);
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i2s_ll_tx_set_ws_width(hal->dev, ws_width);
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_tx_set_half_sample_bit(hal->dev, chan_num * chan_bits / 2);
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#endif
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}
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void i2s_hal_rx_set_channel_style(i2s_hal_context_t *hal, const i2s_hal_config_t *hal_cfg)
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{
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uint32_t chan_num = 2;
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uint32_t chan_bits = hal_cfg->chan_bits;
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uint32_t data_bits = hal_cfg->sample_bits;
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bool is_mono = (hal_cfg->chan_fmt == I2S_CHANNEL_FMT_ONLY_RIGHT) ||
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(hal_cfg->chan_fmt == I2S_CHANNEL_FMT_ONLY_LEFT);
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#if SOC_I2S_SUPPORTS_TDM
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chan_num = hal_cfg->total_chan;
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i2s_ll_rx_set_chan_num(hal->dev, chan_num);
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#endif
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i2s_ll_rx_set_sample_bit(hal->dev, chan_bits, data_bits);
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i2s_ll_rx_enable_mono_mode(hal->dev, is_mono);
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/* Set communication format */
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bool shift_en = hal_cfg->comm_fmt == I2S_COMM_FORMAT_STAND_I2S ? true : false;
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uint32_t ws_width = i2s_hal_get_ws_bit(hal_cfg->comm_fmt, chan_num, chan_bits);
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i2s_ll_rx_enable_msb_shift(hal->dev, shift_en);
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i2s_ll_rx_set_ws_width(hal->dev, ws_width);
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_rx_set_half_sample_bit(hal->dev, chan_num * chan_bits / 2);
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#endif
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}
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void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_hal_config_t *hal_cfg)
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{
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#if SOC_I2S_SUPPORTS_ADC
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if (hal_cfg->mode & I2S_MODE_ADC_BUILT_IN) {
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/* In ADC built-in mode, we need to call i2s_set_adc_mode to initialize the specific ADC channel.
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* In the current stage, we only support ADC1 and single channel mode.
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* In default data mode, the ADC data is in 12-bit resolution mode.
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*/
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i2s_ll_enable_builtin_adc(hal->dev, true);
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return;
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}
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i2s_ll_enable_builtin_adc(hal->dev, false);
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#endif
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#if SOC_I2S_SUPPORTS_DAC
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if (hal_cfg->mode & I2S_MODE_DAC_BUILT_IN) {
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i2s_ll_enable_builtin_dac(hal->dev, true);
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return;
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}
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i2s_ll_enable_builtin_dac(hal->dev, false);
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#endif
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/* Set configurations for TX mode */
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if (hal_cfg->mode & I2S_MODE_TX) {
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i2s_ll_tx_stop(hal->dev);
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i2s_ll_tx_reset(hal->dev);
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i2s_ll_tx_set_slave_mod(hal->dev, (hal_cfg->mode & I2S_MODE_SLAVE) != 0); //TX Slave
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#if SOC_I2S_SUPPORTS_PDM_TX
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if (hal_cfg->mode & I2S_MODE_PDM) {
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/* Set tx pdm mode */
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i2s_hal_tx_set_pdm_mode_default(hal, hal_cfg->sample_rate);
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} else
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#endif
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{
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/* Set tx common mode */
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i2s_hal_tx_set_common_mode(hal, hal_cfg);
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}
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i2s_hal_tx_set_channel_style(hal, hal_cfg);
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}
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/* Set configurations for RX mode */
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if (hal_cfg->mode & I2S_MODE_RX) {
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i2s_ll_rx_stop(hal->dev);
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i2s_ll_rx_reset(hal->dev);
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i2s_ll_rx_set_slave_mod(hal->dev, (hal_cfg->mode & I2S_MODE_SLAVE) != 0); //RX Slave
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#if SOC_I2S_SUPPORTS_PDM_RX
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if (hal_cfg->mode & I2S_MODE_PDM) {
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/* Set rx pdm mode */
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i2s_hal_rx_set_pdm_mode_default(hal);
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} else
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#endif
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{
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/* Set rx common mode */
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i2s_hal_rx_set_common_mode(hal, hal_cfg);
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}
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i2s_hal_rx_set_channel_style(hal, hal_cfg);
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}
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/* Set configurations for full-duplex mode */
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if ((hal_cfg->mode & I2S_MODE_RX) && (hal_cfg->mode & I2S_MODE_TX)) {
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i2s_ll_share_bck_ws(hal->dev, true);
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if (hal_cfg->mode & I2S_MODE_MASTER) {
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i2s_hal_enable_master_fd_mode(hal);
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} else {
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i2s_hal_enable_slave_fd_mode(hal);
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}
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}
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}
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void i2s_hal_start_tx(i2s_hal_context_t *hal)
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{
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_tx_enable_clock(hal->dev);
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#endif
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i2s_ll_tx_start(hal->dev);
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}
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void i2s_hal_start_rx(i2s_hal_context_t *hal)
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{
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_rx_enable_clock(hal->dev);
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#endif
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i2s_ll_rx_start(hal->dev);
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}
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void i2s_hal_stop_tx(i2s_hal_context_t *hal)
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{
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i2s_ll_tx_stop(hal->dev);
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_tx_disable_clock(hal->dev);
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#endif
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}
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void i2s_hal_stop_rx(i2s_hal_context_t *hal)
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{
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i2s_ll_rx_stop(hal->dev);
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#if SOC_I2S_SUPPORTS_TDM
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i2s_ll_rx_disable_clock(hal->dev);
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#endif
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}
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