kopia lustrzana https://github.com/espressif/esp-idf
437 wiersze
14 KiB
C
437 wiersze
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "esp_sleep.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "soc/rtc_periph.h"
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#include "ulp_riscv.h"
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#include "ulp_riscv_lock.h"
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#include "ulp_test_app.h"
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#include "ulp_test_app2.h"
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#include "ulp_test_shared.h"
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#include "unity.h"
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#include <sys/time.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#define ULP_WAKEUP_PERIOD 1000000 // 1 second
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// First ULP firmware
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extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_test_app_bin_start");
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extern const size_t ulp_main_bin_length asm("ulp_test_app_bin_length");
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static bool firmware_loaded = false;
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// Second ULP firmware
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extern const uint8_t ulp_test_app2_bin_start[] asm("_binary_ulp_test_app2_bin_start");
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extern const size_t ulp_test_app2_bin_length asm("ulp_test_app2_bin_length");
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// Faulty ULP firmware
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extern const uint8_t ulp_test_app3_bin_start[] asm("_binary_ulp_test_app3_bin_start");
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extern const size_t ulp_test_app3_bin_length asm("ulp_test_app3_bin_length");
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static void load_and_start_ulp_firmware(const uint8_t* ulp_bin, size_t ulp_bin_len)
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{
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if (!firmware_loaded) {
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TEST_ASSERT(ulp_riscv_load_binary(ulp_bin, ulp_bin_len) == ESP_OK);
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TEST_ASSERT(ulp_set_wakeup_period(0, ULP_WAKEUP_PERIOD) == ESP_OK);
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TEST_ASSERT(ulp_riscv_run() == ESP_OK);
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firmware_loaded = true;
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printf("New ULP firmware loaded\n");
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}
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}
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TEST_CASE("ULP-RISC-V and main CPU are able to exchange data", "[ulp]")
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{
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const uint32_t test_data = 0x12345678;
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struct timeval start, end;
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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/* Setup test data */
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ulp_riscv_test_data_in = test_data ^ XOR_MASK;
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ulp_main_cpu_command = RISCV_READ_WRITE_TEST;
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/* Enter Light Sleep */
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esp_light_sleep_start();
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/* Wait till we receive the correct command response */
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gettimeofday(&start, NULL);
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while (ulp_command_resp != RISCV_READ_WRITE_TEST)
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;
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gettimeofday(&end, NULL);
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printf("Response time %jd ms\n", ((intmax_t)end.tv_sec - (intmax_t)start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000);
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/* Verify test data */
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TEST_ASSERT(ulp_command_resp == RISCV_READ_WRITE_TEST);
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TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
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printf("data out: 0x%" PRIx32 ", expected: 0x%" PRIx32 " \n", ulp_riscv_test_data_out, test_data);
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TEST_ASSERT(test_data == ulp_riscv_test_data_out);
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/* Clear test data */
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ulp_main_cpu_command = RISCV_NO_COMMAND;
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}
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TEST_CASE("ULP-RISC-V is able to wakeup main CPU from light sleep", "[ulp]")
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{
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struct timeval start, end;
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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/* Setup test data */
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ulp_main_cpu_command = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
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/* Enter Light Sleep */
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esp_light_sleep_start();
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/* Wait till we receive the correct command response */
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gettimeofday(&start, NULL);
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while (ulp_command_resp != RISCV_LIGHT_SLEEP_WAKEUP_TEST)
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;
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gettimeofday(&end, NULL);
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printf("Response time 1st: %jd ms\n", ((intmax_t)end.tv_sec - (intmax_t)start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000);
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/* Verify test data */
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TEST_ASSERT(ulp_command_resp == RISCV_LIGHT_SLEEP_WAKEUP_TEST);
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TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
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/* Enter Light Sleep again */
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esp_light_sleep_start();
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/* Wait till we receive the correct command response */
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gettimeofday(&start, NULL);
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while (ulp_command_resp != RISCV_LIGHT_SLEEP_WAKEUP_TEST)
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;
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gettimeofday(&end, NULL);
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printf("Response time 2nd: %jd ms\n", ((intmax_t)end.tv_sec - (intmax_t)start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000);
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/* Verify test data */
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TEST_ASSERT(ulp_command_resp == RISCV_LIGHT_SLEEP_WAKEUP_TEST);
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TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
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/* Clear test data */
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ulp_main_cpu_command = RISCV_NO_COMMAND;
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}
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static bool ulp_riscv_is_running(uint32_t *counter_variable)
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{
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uint32_t start_cnt = *counter_variable;
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/* Wait a few ULP wakeup cycles to ensure ULP has run */
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vTaskDelay((5 * ULP_WAKEUP_PERIOD / 1000) / portTICK_PERIOD_MS);
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uint32_t end_cnt = *counter_variable;
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printf("start run count: %" PRIu32 ", end run count %" PRIu32 "\n", start_cnt, end_cnt);
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/* If the ulp is running the counter should have been incremented */
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return (start_cnt != end_cnt);
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}
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TEST_CASE("ULP-RISC-V can be stopped and resumed from main CPU", "[ulp]")
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{
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
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printf("Stopping the ULP\n");
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ulp_riscv_timer_stop();
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ulp_riscv_halt();
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TEST_ASSERT(!ulp_riscv_is_running(&ulp_riscv_counter));
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printf("Resuming the ULP\n");
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ulp_riscv_timer_resume();
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
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}
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TEST_CASE("ULP-RISC-V can be loaded with and run multiple firmwares", "[ulp]")
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{
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
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printf("Stopping the ULP\n");
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ulp_riscv_timer_stop();
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ulp_riscv_halt();
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TEST_ASSERT(!ulp_riscv_is_running(&ulp_riscv_counter));
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printf("Loading second firmware on the ULP\n");
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firmware_loaded = false;
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load_and_start_ulp_firmware(ulp_test_app2_bin_start, ulp_test_app2_bin_length);
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter2));
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printf("Stopping the ULP\n");
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ulp_riscv_timer_stop();
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ulp_riscv_halt();
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TEST_ASSERT(!ulp_riscv_is_running(&ulp_riscv_counter2));
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printf("Loading the first firmware again on the ULP\n");
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firmware_loaded = false;
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
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}
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TEST_CASE("ULP-RISC-V can be reloaded with a good fimware after a crash", "[ulp]")
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{
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
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printf("Stopping the ULP\n");
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ulp_riscv_timer_stop();
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ulp_riscv_halt();
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TEST_ASSERT(!ulp_riscv_is_running(&ulp_riscv_counter));
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/* Enable ULP wakeup */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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printf("Loading faulty firmware on the ULP and go into light sleep\n");
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firmware_loaded = false;
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load_and_start_ulp_firmware(ulp_test_app3_bin_start, ulp_test_app3_bin_length);
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esp_light_sleep_start();
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/* Verify that main CPU wakes up by a COCPU trap signal trigger */
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esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
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TEST_ASSERT(cause != ESP_SLEEP_WAKEUP_COCPU);
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printf("Resetting the ULP\n");
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ulp_riscv_reset();
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esp_rom_delay_us(20);
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printf("Loading the good firmware on ULP\n");
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firmware_loaded = false;
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
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}
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TEST_CASE("ULP-RISC-V can stop itself and be resumed from the main CPU", "[ulp]")
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{
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volatile riscv_test_commands_t *command_resp = (riscv_test_commands_t*)&ulp_command_resp;
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
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printf("Stopping the ULP\n");
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/* Setup test data */
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ulp_main_cpu_command = RISCV_STOP_TEST;
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while (*command_resp != RISCV_STOP_TEST) {
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}
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/* Wait a bit to ensure ULP finished shutting down */
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vTaskDelay(100 / portTICK_PERIOD_MS);
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TEST_ASSERT(!ulp_riscv_is_running(&ulp_riscv_counter));
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printf("Resuming the ULP\n");
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ulp_main_cpu_command = RISCV_NO_COMMAND;
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ulp_riscv_timer_resume();
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TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
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}
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TEST_CASE("ULP-RISC-V mutex", "[ulp]")
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{
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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/* Setup test data */
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ulp_riscv_incrementer = 0;
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ulp_main_cpu_reply = RISCV_NO_COMMAND;
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ulp_main_cpu_command = RISCV_MUTEX_TEST;
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ulp_riscv_lock_t *lock = (ulp_riscv_lock_t*)&ulp_lock;
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for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) {
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ulp_riscv_lock_acquire(lock);
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ulp_riscv_incrementer++;
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ulp_riscv_lock_release(lock);
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}
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while(ulp_main_cpu_reply != RISCV_COMMAND_OK) {
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// Wait for ULP to finish
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}
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/* If the variable is protected there should be no race conditions
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results should be the sum of increments made by ULP and by main CPU
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*/
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TEST_ASSERT_EQUAL(2*MUTEX_TEST_ITERATIONS, ulp_riscv_incrementer);
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}
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static void do_ulp_wakeup_deepsleep(riscv_test_commands_t ulp_cmd, bool rtc_periph_pd)
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{
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if (!rtc_periph_pd) {
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// Force RTC peripheral power domain to be on
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esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
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}
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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/* Setup test data */
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ulp_main_cpu_command = ulp_cmd;
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/* Enter Deep Sleep */
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esp_deep_sleep_start();
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UNITY_TEST_FAIL(__LINE__, "Should not get here!");
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}
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static void check_reset_reason_ulp_wakeup(void)
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{
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TEST_ASSERT_EQUAL(ESP_SLEEP_WAKEUP_ULP, esp_sleep_get_wakeup_cause());
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}
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static void do_ulp_wakeup_after_long_delay_deepsleep(void)
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{
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do_ulp_wakeup_deepsleep(RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST, true);
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}
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/* Certain erroneous wake-up triggers happen only after a sleeping for a few seconds */
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TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a long delay", "[ulp]",
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do_ulp_wakeup_after_long_delay_deepsleep,
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check_reset_reason_ulp_wakeup);
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static void do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on(void)
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{
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do_ulp_wakeup_deepsleep(RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST, false);
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}
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TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a long delay, RTC periph powerup", "[ulp]",
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do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on,
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check_reset_reason_ulp_wakeup);
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static void do_ulp_wakeup_after_short_delay_deepsleep(void)
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{
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do_ulp_wakeup_deepsleep(RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST, true);
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}
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TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a short delay", "[ulp]",
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do_ulp_wakeup_after_short_delay_deepsleep,
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check_reset_reason_ulp_wakeup);
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static void do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on(void)
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{
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do_ulp_wakeup_deepsleep(RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST, false);
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}
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TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a short delay, RTC periph powerup", "[ulp]",
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do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on,
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check_reset_reason_ulp_wakeup);
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typedef struct {
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SemaphoreHandle_t ulp_isr_sw_sem;
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SemaphoreHandle_t ulp_isr_trap_sem;
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} TestSemaphore_t;
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static void ulp_riscv_isr(void *arg)
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{
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BaseType_t yield = 0;
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TestSemaphore_t *sem = (TestSemaphore_t *)arg;
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uint32_t status = READ_PERI_REG(RTC_CNTL_INT_ST_REG);
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if (status & ULP_RISCV_SW_INT) {
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xSemaphoreGiveFromISR(sem->ulp_isr_sw_sem, &yield);
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} else if (status & ULP_RISCV_TRAP_INT) {
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xSemaphoreGiveFromISR(sem->ulp_isr_trap_sem, &yield);
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}
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if (yield) {
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portYIELD_FROM_ISR();
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}
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}
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TEST_CASE("ULP-RISC-V interrupt signals can be handled via ISRs on the main core", "[ulp]")
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{
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/* Create test semaphores */
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TestSemaphore_t test_sem_cfg;
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test_sem_cfg.ulp_isr_sw_sem = xSemaphoreCreateBinary();
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TEST_ASSERT_NOT_NULL(test_sem_cfg.ulp_isr_sw_sem);
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test_sem_cfg.ulp_isr_trap_sem = xSemaphoreCreateBinary();
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TEST_ASSERT_NOT_NULL(test_sem_cfg.ulp_isr_trap_sem);
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/* Register ULP RISC-V signal ISR */
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TEST_ASSERT_EQUAL(ESP_OK, ulp_riscv_isr_register(ulp_riscv_isr, (void *)&test_sem_cfg,
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(ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT)));
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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printf("Loading good ULP firmware\n");
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firmware_loaded = false;
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load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
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/* Setup test data. We only need the ULP to send a wakeup signal to the main CPU. */
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ulp_main_cpu_command = RISCV_READ_WRITE_TEST;
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/* Wait for the ISR to be called */
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printf("Waiting for ULP wakeup signal ...\n");
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TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(test_sem_cfg.ulp_isr_sw_sem, portMAX_DELAY));
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printf("ULP wakeup signal interrupt triggered\n");
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/* Reset the ULP command */
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ulp_main_cpu_command = RISCV_NO_COMMAND;
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/* Load ULP RISC-V with faulty firmware and restart the ULP RISC-V Coprocessor.
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* This should cause a cocpu trap signal interrupt.
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*/
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printf("Loading faulty ULP firmware\n");
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firmware_loaded = false;
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load_and_start_ulp_firmware(ulp_test_app3_bin_start, ulp_test_app3_bin_length);
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/* Wait for the ISR to be called */
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printf("Waiting for ULP trap signal ...\n");
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TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(test_sem_cfg.ulp_isr_trap_sem, portMAX_DELAY));
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printf("ULP trap signal interrupt triggered\n");
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/* Deregister the ISR */
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TEST_ASSERT_EQUAL(ESP_OK, ulp_riscv_isr_deregister(ulp_riscv_isr, (void *)&test_sem_cfg,
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(ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT)));
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/* Delete test semaphores */
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vSemaphoreDelete(test_sem_cfg.ulp_isr_sw_sem);
|
|
vSemaphoreDelete(test_sem_cfg.ulp_isr_trap_sem);
|
|
|
|
/* Make sure ULP has a good firmware running before exiting the test */
|
|
ulp_riscv_reset();
|
|
firmware_loaded = false;
|
|
load_and_start_ulp_firmware(ulp_main_bin_start, ulp_main_bin_length);
|
|
}
|