kopia lustrzana https://github.com/espressif/esp-idf
186 wiersze
5.0 KiB
C
186 wiersze
5.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "spi_flash_defs.h"
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//MXIC OPI mode needs two bytes of command - 2nd byte is the inversion of the command (1st) byte. S3 HW send LSB first
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#define MXIC_CMD16(cmd8) ( (uint8_t)(cmd8) | ((uint8_t)(~(cmd8)) << 8) )
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#define OPI_CMD_FORMAT_MXIC_STR() { \
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.rdid = { \
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.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_RDID), \
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.addr = 0, \
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.addr_bit_len = 4*8, \
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.dummy_bit_len = 4, \
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.data_bit_len = 4 * 8, \
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.cs_sel = 0x1, \
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.is_pe = 0, \
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}, \
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.rdsr = { \
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.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_RDSR), \
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.addr = 0, \
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.addr_bit_len = 4*8, \
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.dummy_bit_len = 4, \
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.data_bit_len = 1 * 8, \
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.cs_sel = 0x1, \
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.is_pe = 0, \
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}, \
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.wren = { \
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.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_WREN), \
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.addr = 0, \
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.addr_bit_len = 0, \
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.dummy_bit_len = 0, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 0, \
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}, \
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.se = { \
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.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_SECTOR_ERASE_4B), \
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.addr = 0, \
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.addr_bit_len = 32, \
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.dummy_bit_len = 0, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 1, \
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}, \
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.be64k = { \
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.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_LARGE_BLOCK_ERASE_4B), \
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.addr = 0, \
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.addr_bit_len = 32, \
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.dummy_bit_len = 0, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 1, \
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}, \
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.read = { \
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.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_8READ), \
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.addr = 0, \
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.addr_bit_len = 32, \
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.dummy_bit_len = 20, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 0, \
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}, \
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.pp = { \
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.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_PROGRAM_PAGE_4B), \
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.addr = 0, \
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.addr_bit_len = 32, \
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.dummy_bit_len = 0, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 1, \
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}, \
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.cache_rd_cmd = { \
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.addr_bit_len = 32, \
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.dummy_bit_len = 20, \
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.cmd = MXIC_CMD16(CMD_8READ), \
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.cmd_bit_len = 16, \
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.var_dummy_en = 1, \
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} \
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}
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#define OPI_CMD_FORMAT_MXIC_DTR() { \
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.rdid = { \
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.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_RDID), \
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.addr = 0, \
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.addr_bit_len = 4*8, \
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.dummy_bit_len = 4*2, \
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.data_bit_len = 4 * 8, \
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.cs_sel = 0x1, \
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.is_pe = 0, \
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}, \
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.rdsr = { \
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.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_RDSR), \
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.addr = 0, \
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.addr_bit_len = 4*8, \
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.dummy_bit_len = 4*2, \
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.data_bit_len = 2 * 8, \
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.cs_sel = 0x1, \
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.is_pe = 0, \
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}, \
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.wren = { \
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.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_WREN), \
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.addr = 0, \
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.addr_bit_len = 0, \
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.dummy_bit_len = 0, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 0, \
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}, \
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.se = { \
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.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_SECTOR_ERASE_4B), \
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.addr = 0, \
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.addr_bit_len = 32, \
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.dummy_bit_len = 0, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 1, \
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}, \
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.be64k = { \
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.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_LARGE_BLOCK_ERASE_4B), \
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.addr = 0, \
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.addr_bit_len = 32, \
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.dummy_bit_len = 0, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 1, \
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}, \
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.read = { \
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.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_8DTRD), \
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.addr = 0, \
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.addr_bit_len = 32, \
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.dummy_bit_len = 20*2, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 0, \
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}, \
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.pp = { \
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.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
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.cmd_bit_len = 16, \
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.cmd = MXIC_CMD16(CMD_PROGRAM_PAGE_4B), \
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.addr = 0, \
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.addr_bit_len = 32, \
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.dummy_bit_len = 0, \
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.data_bit_len = 0, \
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.cs_sel = 0x1, \
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.is_pe = 1, \
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}, \
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.cache_rd_cmd = { \
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.addr_bit_len = 32, \
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.dummy_bit_len = 20*2, \
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.cmd = MXIC_CMD16(CMD_8DTRD), \
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.cmd_bit_len = 16, \
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.var_dummy_en = 1, \
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} \
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}
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