kopia lustrzana https://github.com/espressif/esp-idf
338 wiersze
22 KiB
C
338 wiersze
22 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_UHCI_STRUCT_H_
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#define _SOC_UHCI_STRUCT_H_
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typedef volatile struct {
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union {
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struct {
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uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/
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uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/
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uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/
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uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/
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uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/
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uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/
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uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/
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uint32_t out_no_restart_clr: 1; /*don't use*/
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uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/
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uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/
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uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/
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uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/
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uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/
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uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/
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uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/
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uint32_t mem_trans_en: 1;
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uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/
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uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/
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uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/
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uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/
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uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/
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uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/
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uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/
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uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/
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uint32_t tx_start: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
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uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/
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uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/
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uint32_t in_done: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/
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uint32_t in_suc_eof: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/
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uint32_t in_err_eof: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/
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uint32_t out_done: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/
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uint32_t out_eof: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/
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uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/
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uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/
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uint32_t in_dscr_empty: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/
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uint32_t outlink_eof_err: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/
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uint32_t out_total_eof: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/
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uint32_t send_s_q: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/
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uint32_t send_a_q: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/
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uint32_t dma_in_fifo_full_wm: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t rx_start: 1;
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uint32_t tx_start: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t outlink_eof_err: 1;
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uint32_t out_total_eof: 1;
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uint32_t send_s_q: 1;
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uint32_t send_a_q: 1;
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uint32_t dma_in_fifo_full_wm: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t rx_start: 1;
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uint32_t tx_start: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t outlink_eof_err: 1;
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uint32_t out_total_eof: 1;
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uint32_t send_s_q: 1;
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uint32_t send_a_q: 1;
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uint32_t dma_in_fifo_full_wm: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t rx_start: 1;
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uint32_t tx_start: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t outlink_eof_err: 1;
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uint32_t out_total_eof: 1;
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uint32_t send_s_q: 1;
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uint32_t send_a_q: 1;
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uint32_t dma_in_fifo_full_wm: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/
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uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/
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uint32_t reserved2: 30;
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};
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uint32_t val;
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} dma_out_status;
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union {
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struct {
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uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/
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uint32_t reserved9: 7;
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uint32_t fifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/
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uint32_t reserved17:15;
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};
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uint32_t val;
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} dma_out_push;
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union {
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struct {
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uint32_t full: 1;
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uint32_t empty: 1;
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uint32_t reserved2: 2;
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uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/
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uint32_t reserved7: 25;
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};
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uint32_t val;
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} dma_in_status;
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union {
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struct {
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uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/
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uint32_t reserved12: 4;
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uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} dma_in_pop;
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union {
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struct {
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uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/
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uint32_t reserved20: 8;
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uint32_t stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/
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uint32_t start: 1; /*Set this bit to start dealing with the out link descriptors.*/
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uint32_t restart: 1; /*Set this bit to mount on new out link descriptors*/
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uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/
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};
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uint32_t val;
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} dma_out_link;
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union {
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struct {
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uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/
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uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/
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uint32_t reserved21: 7;
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uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/
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uint32_t start: 1; /*Set this bit to start dealing with the in link descriptors.*/
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uint32_t restart: 1; /*Set this bit to mount on new in link descriptors*/
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uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/
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};
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uint32_t val;
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} dma_in_link;
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union {
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struct {
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uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/
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uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/
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uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/
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uint32_t save_head: 1; /*Set this bit to save packet header .*/
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uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/
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uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/
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uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/
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uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/
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uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/
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uint32_t dma_in_fifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} conf1;
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uint32_t state0; /**/
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uint32_t state1; /**/
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uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/
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uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/
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uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/
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uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/
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union {
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struct {
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uint32_t test_mode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
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uint32_t reserved3: 1;
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uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} ahb_test;
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uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/
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uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/
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uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/
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uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/
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uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/
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uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/
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union {
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struct {
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uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/
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uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/
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uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/
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uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/
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uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/
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uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/
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uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/
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uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} escape_conf;
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union {
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struct {
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uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/
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uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/
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uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/
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uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/
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uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/
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uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} hung_conf;
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uint32_t ack_num; /**/
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uint32_t rx_head; /*This register stores the packet header received by DMA*/
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union {
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struct {
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uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/
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uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/
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uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/
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uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} quick_sent;
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struct{
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uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
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} q_data[7];
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union {
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struct {
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uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/
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uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/
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uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf0;
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union {
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struct {
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uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/
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uint32_t seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/
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uint32_t seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf1;
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union {
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struct {
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uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/
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uint32_t seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/
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uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf2;
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union {
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struct {
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uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/
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uint32_t seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/
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uint32_t seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf3;
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union {
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struct {
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uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/
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uint32_t reserved13:19;
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};
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uint32_t val;
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} pkt_thres;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t date; /*version information*/
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} uhci_dev_t;
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extern uhci_dev_t UHCI0;
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extern uhci_dev_t UHCI1;
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#endif /* _SOC_UHCI_STRUCT_H_ */
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