kopia lustrzana https://github.com/espressif/esp-idf
430 wiersze
18 KiB
Plaintext
430 wiersze
18 KiB
Plaintext
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menu "ESP System Settings"
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choice ESP_SYSTEM_PANIC
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prompt "Panic handler behaviour"
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default ESP_SYSTEM_PANIC_PRINT_REBOOT
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help
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If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
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invoked. Configure the panic handler's action here.
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config ESP_SYSTEM_PANIC_PRINT_HALT
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bool "Print registers and halt"
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help
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Outputs the relevant registers over the serial port and halt the
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processor. Needs a manual reset to restart.
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config ESP_SYSTEM_PANIC_PRINT_REBOOT
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bool "Print registers and reboot"
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help
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Outputs the relevant registers over the serial port and immediately
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reset the processor.
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config ESP_SYSTEM_PANIC_SILENT_REBOOT
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bool "Silent reboot"
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help
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Just resets the processor without outputting anything
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config ESP_SYSTEM_PANIC_GDBSTUB
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bool "Invoke GDBStub"
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select ESP_GDBSTUB_ENABLED
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help
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Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
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of the crash.
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endchoice
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config ESP_SYSTEM_SINGLE_CORE_MODE
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bool
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default n
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help
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Only initialize and use the main core.
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config ESP_SYSTEM_RTC_EXT_XTAL
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# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
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# e.g. It will be selected on when ESP32_RTC_CLK_SRC_EXT_CRYS is on
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bool
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default n
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config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
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int "Bootstrap cycles for external 32kHz crystal"
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depends on ESP_SYSTEM_RTC_EXT_XTAL
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default 5 if IDF_TARGET_ESP32
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default 0
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range 0 32768
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help
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To reduce the startup time of an external RTC crystal,
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we bootstrap it with a 32kHz square wave for a fixed number of cycles.
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Setting 0 will disable bootstrapping (if disabled, the crystal may take
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longer to start up or fail to oscillate under some conditions).
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If this value is too high, a faulty crystal may initially start and then fail.
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If this value is too low, an otherwise good crystal may not start.
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To accurately determine if the crystal has started,
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set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
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config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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bool
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default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE
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default y if IDF_TARGET_ESP32S2
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default y if IDF_TARGET_ESP32C3
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default y if IDF_TARGET_ESP32S3
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config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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bool "Enable RTC fast memory for dynamic allocations"
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default y if IDF_TARGET_ESP32
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default y if IDF_TARGET_ESP32S2
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default y if IDF_TARGET_ESP32C3
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default n if IDF_TARGET_ESP32S3 # TODO
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depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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help
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This config option allows to add RTC fast memory region to system heap with capability
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similar to that of DRAM region but without DMA. This memory will be consumed first per
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heap initialization order by early startup services and scheduler related code. Speed
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wise RTC fast memory operates on APB clock and hence does not have much performance impact.
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config ESP_SYSTEM_PD_FLASH
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bool "PD flash at light sleep when there is no SPIRAM"
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depends on !SPIRAM
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default y
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help
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If enabled, chip will try to power down flash at light sleep, which costs more time when chip wakes up.
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Can only be enabled if there is no SPIRAM configured. This option will in fact consider VDD_SDIO auto power
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value (ESP_PD_OPTION_AUTO) as OFF. Also, it is possible to force a power domain to stay ON during light
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sleep by using esp_sleep_pd_config() function.
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config ESP_SYSTEM_PM_POWER_DOWN_CPU
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bool "Power down CPU in light sleep"
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depends on IDF_TARGET_ESP32C3
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default y
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help
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If enabled, the CPU will be powered down in light sleep. Enabling this option will consume
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1.68 KB of internal RAM and will reduce sleep current consumption by about 100 uA.
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menu "Memory protection"
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config ESP_SYSTEM_MEMPROT_FEATURE
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bool "Enable memory protection"
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depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S2
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default "y"
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help
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If enabled, the permission control module watches all the memory access and fires the panic handler
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if a permission violation is detected. This feature automatically splits
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the SRAM memory into data and instruction segments and sets Read/Execute permissions
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for the instruction part (below given splitting address) and Read/Write permissions
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for the data part (above the splitting address). The memory protection is effective
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on all access through the IRAM0 and DRAM0 buses.
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config ESP_SYSTEM_MEMPROT_FEATURE_LOCK
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depends on ESP_SYSTEM_MEMPROT_FEATURE
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bool "Lock memory protection settings"
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default "y"
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help
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Once locked, memory protection settings cannot be changed anymore.
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The lock is reset only on the chip startup.
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endmenu # Memory protection
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config ESP_SYSTEM_EVENT_QUEUE_SIZE
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int "System event queue size"
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default 32
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help
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Config system event queue size in different application.
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config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
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int "Event loop task stack size"
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default 2304
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help
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Config system event task stack size in different application.
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config ESP_MAIN_TASK_STACK_SIZE
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int "Main task stack size"
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default 3584
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help
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Configure the "main task" stack size. This is the stack of the task
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which calls app_main(). If app_main() returns then this task is deleted
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and its stack memory is freed.
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choice ESP_MAIN_TASK_AFFINITY
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prompt "Main task core affinity"
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default ESP_MAIN_TASK_AFFINITY_CPU0
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help
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Configure the "main task" core affinity. This is the used core of the task
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which calls app_main(). If app_main() returns then this task is deleted.
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config ESP_MAIN_TASK_AFFINITY_CPU0
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bool "CPU0"
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config ESP_MAIN_TASK_AFFINITY_CPU1
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bool "CPU1"
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depends on !FREERTOS_UNICORE
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config ESP_MAIN_TASK_AFFINITY_NO_AFFINITY
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bool "No affinity"
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endchoice
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config ESP_MAIN_TASK_AFFINITY
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hex
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default 0x0 if ESP_MAIN_TASK_AFFINITY_CPU0
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default 0x1 if ESP_MAIN_TASK_AFFINITY_CPU1
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default FREERTOS_NO_AFFINITY if ESP_MAIN_TASK_AFFINITY_NO_AFFINITY
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config ESP_MINIMAL_SHARED_STACK_SIZE
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int "Minimal allowed size for shared stack"
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default 2048
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help
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Minimal value of size, in bytes, accepted to execute a expression
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with shared stack.
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choice ESP_CONSOLE_UART
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prompt "Channel for console output"
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default ESP_CONSOLE_UART_DEFAULT
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help
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Select where to send console output (through stdout and stderr).
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- Default is to use UART0 on pre-defined GPIOs.
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- If "Custom" is selected, UART0 or UART1 can be chosen,
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and any pins can be selected.
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- If "None" is selected, there will be no console output on any UART, except
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for initial output from ROM bootloader. This ROM output can be suppressed by
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GPIO strapping or EFUSE, refer to chip datasheet for details.
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- On chips with USB peripheral, "USB CDC" option redirects output to the
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CDC port. This option uses the CDC driver in the chip ROM.
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This option is incompatible with TinyUSB stack.
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config ESP_CONSOLE_UART_DEFAULT
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bool "Default: UART0"
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config ESP_CONSOLE_USB_CDC
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bool "USB CDC"
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# The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general.
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# && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB.
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depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !USB_ENABLED
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config ESP_CONSOLE_UART_CUSTOM
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bool "Custom UART"
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config ESP_CONSOLE_NONE
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bool "None"
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endchoice
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# Internal option, indicates that console UART is used (and not USB, for example)
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config ESP_CONSOLE_UART
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bool
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default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM
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config ESP_CONSOLE_MULTIPLE_UART
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bool
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default y if !IDF_TARGET_ESP32C3
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choice ESP_CONSOLE_UART_NUM
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prompt "UART peripheral to use for console output (0-1)"
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depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART
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default ESP_CONSOLE_UART_CUSTOM_NUM_0
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help
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This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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Due to an ESP32 ROM bug, UART2 is not supported for console output
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via esp_rom_printf.
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config ESP_CONSOLE_UART_CUSTOM_NUM_0
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bool "UART0"
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config ESP_CONSOLE_UART_CUSTOM_NUM_1
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bool "UART1"
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endchoice
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config ESP_CONSOLE_UART_NUM
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int
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default 0 if ESP_CONSOLE_UART_DEFAULT
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default 0 if !ESP_CONSOLE_MULTIPLE_UART
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default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
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default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
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default -1 if !ESP_CONSOLE_UART
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config ESP_CONSOLE_UART_TX_GPIO
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int "UART TX on GPIO#"
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depends on ESP_CONSOLE_UART_CUSTOM
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range 0 46
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default 1 if IDF_TARGET_ESP32
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default 21 if IDF_TARGET_ESP32C3
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default 43
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help
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This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including
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boot log output and default standard output and standard error of the app).
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_UART_RX_GPIO
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int "UART RX on GPIO#"
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depends on ESP_CONSOLE_UART_CUSTOM
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range 0 46
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default 3 if IDF_TARGET_ESP32
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default 20 if IDF_TARGET_ESP32C3
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default 44
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help
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This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including
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default default standard input of the app).
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Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_UART_BAUDRATE
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int
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prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
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depends on ESP_CONSOLE_UART
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default 115200
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range 1200 4000000 if !PM_ENABLE
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range 1200 1000000 if PM_ENABLE
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help
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This baud rate is used by both the ESP-IDF Bootloader and the app (including
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boot log output and default standard input/output/error of the app).
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The app's maximum baud rate depends on the UART clock source. If Power Management is disabled,
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the UART clock source is the APB clock and all baud rates in the available range will be sufficiently
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accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided
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from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be
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accurate.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE
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int "Size of USB CDC RX buffer"
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depends on ESP_CONSOLE_USB_CDC
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default 64
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range 4 16384
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help
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Set the size of USB CDC RX buffer. Increase the buffer size if your application
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is often receiving data over USB CDC.
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config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
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bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC"
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depends on ESP_CONSOLE_USB_CDC
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default n
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help
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If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
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Disabling this option saves about 1kB or RAM.
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config ESP_INT_WDT
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bool "Interrupt watchdog"
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default y
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help
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This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
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either because a task turned off interrupts and did not turn them on for a long time, or because an
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interrupt handler did not return. It will try to invoke the panic handler first and failing that
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reset the SoC.
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config ESP_INT_WDT_TIMEOUT_MS
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int "Interrupt watchdog timeout (ms)"
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depends on ESP_INT_WDT
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default 300 if !ESP32_SPIRAM_SUPPORT
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default 800 if ESP32_SPIRAM_SUPPORT
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range 10 10000
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help
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The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
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config ESP_INT_WDT_CHECK_CPU1
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bool "Also watch CPU1 tick interrupt"
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depends on ESP_INT_WDT && !FREERTOS_UNICORE
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default y
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help
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Also detect if interrupts on CPU 1 are disabled for too long.
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config ESP_TASK_WDT
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bool "Initialize Task Watchdog Timer on startup"
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default y
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help
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The Task Watchdog Timer can be used to make sure individual tasks are still
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running. Enabling this option will cause the Task Watchdog Timer to be
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initialized automatically at startup. The Task Watchdog timer can be
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initialized after startup as well (see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_PANIC
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bool "Invoke panic handler on Task Watchdog timeout"
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depends on ESP_TASK_WDT
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default n
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help
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If this option is enabled, the Task Watchdog Timer will be configured to
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trigger the panic handler when it times out. This can also be configured
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at run time (see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_TIMEOUT_S
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int "Task Watchdog timeout period (seconds)"
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depends on ESP_TASK_WDT
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range 1 60
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default 5
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help
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Timeout period configuration for the Task Watchdog Timer in seconds.
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This is also configurable at run time (see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
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bool "Watch CPU0 Idle Task"
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depends on ESP_TASK_WDT
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default y
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help
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If this option is enabled, the Task Watchdog Timer will watch the CPU0
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Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
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of CPU starvation as the Idle Task not being called is usually a symptom of
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CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
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tasks depend on the Idle Task getting some runtime every now and then.
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config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
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bool "Watch CPU1 Idle Task"
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depends on ESP_TASK_WDT && !FREERTOS_UNICORE
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default y
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help
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If this option is enabled, the Task Wtachdog Timer will wach the CPU1
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Idle Task.
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config ESP_IPC_TASK_STACK_SIZE
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int "Inter-Processor Call (IPC) task stack size"
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range 512 65536 if !APPTRACE_ENABLE
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range 2048 65536 if APPTRACE_ENABLE
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default 2048 if APPTRACE_ENABLE
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default 1024
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help
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Configure the IPC tasks stack size. One IPC task runs on each core
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(in dual core mode), and allows for cross-core function calls.
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See IPC documentation for more details.
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The default stack size should be enough for most common use cases.
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It can be shrunk if you are sure that you do not use any custom
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IPC functionality.
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config ESP_IPC_USES_CALLERS_PRIORITY
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bool "IPC runs at caller's priority"
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default y
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depends on !FREERTOS_UNICORE
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help
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If this option is not enabled then the IPC task will keep behavior
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same as prior to that of ESP-IDF v4.0, and hence IPC task will run
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at (configMAX_PRIORITIES - 1) priority.
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config ESP_PANIC_HANDLER_IRAM
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bool "Place panic handler code in IRAM"
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default n
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help
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If this option is disabled (default), the panic handler code is placed in flash not IRAM.
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This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
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automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
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risk, if the flash cache status is also corrupted during the crash.
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If this option is enabled, the panic handler code is placed in IRAM. This allows the panic
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handler to run without needing to re-enable cache first. This may be necessary to debug some
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complex issues with crashes while flash cache is disabled (for example, when writing to
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SPI flash.)
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config ESP_DEBUG_STUBS_ENABLE
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bool
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default COMPILER_OPTIMIZATION_LEVEL_DEBUG
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depends on !ESP32_TRAX && !ESP32S2_TRAX
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help
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Debug stubs are used by OpenOCD to execute pre-compiled onboard code
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which does some useful debugging stuff, e.g. GCOV data dump.
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endmenu # ESP System Settings
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