kopia lustrzana https://github.com/espressif/esp-idf
105 wiersze
4.3 KiB
C
105 wiersze
4.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <assert.h>
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#include "soc/cpu.h"
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void esp_cpu_configure_region_protection(void)
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{
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/* Notes on implementation:
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*
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* 1) Note: ESP32-C3 CPU doesn't support overlapping PMP regions
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*
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* 2) Therefore, we use TOR (top of range) entries to map the whole address
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* space, bottom to top.
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*
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* 3) There are not enough entries to describe all the memory regions 100% accurately.
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*
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* 4) This means some gaps (invalid memory) are accessible. Priority for extending regions
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* to cover gaps is to extend read-only or read-execute regions or read-only regions only
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* (executing unmapped addresses should always fault with invalid instruction, read-only means
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* stores will correctly fault even if reads may return some invalid value.)
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*
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* 5) Entries are grouped in order with some static asserts to try and verify everything is
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* correct.
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*/
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const unsigned NONE = PMP_L | PMP_TOR;
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const unsigned R = PMP_L | PMP_TOR | PMP_R;
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const unsigned RW = PMP_L | PMP_TOR | PMP_R | PMP_W;
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const unsigned RX = PMP_L | PMP_TOR | PMP_R | PMP_X;
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const unsigned RWX = PMP_L | PMP_TOR | PMP_R | PMP_W | PMP_X;
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// 1. Gap at bottom of address space
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PMP_ENTRY_SET(0, SOC_DEBUG_LOW, NONE);
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// 2. Debug region
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PMP_ENTRY_SET(1, SOC_DEBUG_HIGH, RWX);
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_Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region");
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// 3. Gap between debug region & DROM (flash cache)
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PMP_ENTRY_SET(2, SOC_DROM_LOW, NONE);
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_Static_assert(SOC_DEBUG_HIGH < SOC_DROM_LOW, "Invalid PMP entry order");
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// 4. DROM (flash cache)
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// 5. Gap between DROM & DRAM
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// (Note: To save PMP entries these two are merged into one read-only region)
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PMP_ENTRY_SET(3, SOC_DRAM_LOW, R);
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_Static_assert(SOC_DROM_LOW < SOC_DROM_HIGH, "Invalid DROM region");
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_Static_assert(SOC_DROM_HIGH < SOC_DRAM_LOW, "Invalid PMP entry order");
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// 6. DRAM
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PMP_ENTRY_SET(4, SOC_DRAM_HIGH, RW);
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_Static_assert(SOC_DRAM_LOW < SOC_DRAM_HIGH, "Invalid DRAM region");
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// 7. Gap between DRAM and Mask DROM
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// 8. Mask DROM
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// (Note: to save PMP entries these two are merged into one read-only region)
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PMP_ENTRY_SET(5, SOC_DROM_MASK_HIGH, R);
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_Static_assert(SOC_DRAM_HIGH < SOC_DROM_MASK_LOW, "Invalid PMP entry order");
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_Static_assert(SOC_DROM_MASK_LOW < SOC_DROM_MASK_HIGH, "Invalid mask DROM region");
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// 9. Gap between mask DROM and mask IROM
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// 10. Mask IROM
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// (Note: to save PMP entries these two are merged into one RX region)
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PMP_ENTRY_SET(6, SOC_IROM_MASK_HIGH, RX);
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_Static_assert(SOC_DROM_MASK_HIGH < SOC_IROM_MASK_LOW, "Invalid PMP entry order");
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_Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid mask IROM region");
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// 11. Gap between mask IROM & IRAM
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PMP_ENTRY_SET(7, SOC_IRAM_LOW, NONE);
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_Static_assert(SOC_IROM_MASK_HIGH < SOC_IRAM_LOW, "Invalid PMP entry order");
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// 12. IRAM
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PMP_ENTRY_SET(8, SOC_IRAM_HIGH, RWX);
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_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid IRAM region");
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// 13. Gap between IRAM and IROM
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// 14. IROM (flash cache)
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// (Note: to save PMP entries these two are merged into one RX region)
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PMP_ENTRY_SET(9, SOC_IROM_HIGH, RX);
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_Static_assert(SOC_IRAM_HIGH < SOC_IROM_LOW, "Invalid PMP entry order");
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_Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid IROM region");
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// 15. Gap between IROM & RTC slow memory
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PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE);
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_Static_assert(SOC_IROM_HIGH < SOC_RTC_IRAM_LOW, "Invalid PMP entry order");
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// 16. RTC fast memory
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PMP_ENTRY_SET(11, SOC_RTC_IRAM_HIGH, RWX);
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_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
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// 17. Gap between RTC fast memory & peripheral addresses
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PMP_ENTRY_SET(12, SOC_PERIPHERAL_LOW, NONE);
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_Static_assert(SOC_RTC_IRAM_HIGH < SOC_PERIPHERAL_LOW, "Invalid PMP entry order");
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// 18. Peripheral addresses
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PMP_ENTRY_SET(13, SOC_PERIPHERAL_HIGH, RW);
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_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
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// 19. End of address space
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PMP_ENTRY_SET(14, UINT32_MAX, NONE); // all but last 4 bytes
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PMP_ENTRY_SET(15, UINT32_MAX, PMP_L | PMP_NA4); // last 4 bytes
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}
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