kopia lustrzana https://github.com/espressif/esp-idf
341 wiersze
15 KiB
C
341 wiersze
15 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/efuse_periph.h"
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#include "soc/gpio_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/extmem_reg.h"
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#include "soc/system_reg.h"
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#include "hal/efuse_hal.h"
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#include "regi2c_ctrl.h"
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#include "soc/regi2c_dig_reg.h"
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#include "soc/regi2c_lp_bias.h"
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#include "esp_hw_log.h"
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#include "esp_efuse.h"
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#include "esp_efuse_table.h"
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static const char *TAG = "rtc_init";
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static void set_ocode_by_efuse(int calib_version);
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static void calibrate_ocode(void);
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static void set_rtc_dig_dbias(void);
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void rtc_init(rtc_config_t cfg)
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{
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
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// set default powerup & wait time
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rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
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if (cfg.cali_ocode) {
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uint32_t rtc_calib_version = 0;
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
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if (err != ESP_OK) {
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rtc_calib_version = 0;
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ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
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}
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if (rtc_calib_version == 1) {
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set_ocode_by_efuse(rtc_calib_version);
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} else {
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calibrate_ocode();
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}
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}
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set_rtc_dig_dbias();
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if (cfg.clkctl_init) {
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//clear CMMU clock force on
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CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
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//clear tag clock force on
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CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);
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//clear register clock force on
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CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN);
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CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN);
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}
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if (cfg.pwrctl_init) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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//cancel xtal force pu if no need to force power up
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//cannot cancel xtal force pu if pll is force power on
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if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
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}
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// force pd APLL
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
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//open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
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//cancel bbpll force pu if setting no force power up
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if (!cfg.bbpll_fpu) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
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}
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
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if (cfg.rtc_dboost_fpd) {
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SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
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}
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//clear i2c_reset_protect pd force, need tested in low temperature.
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//CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD);
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/* If this mask is enabled, all soc memories cannot enter power down mode */
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/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
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CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
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/* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
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/* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
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rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0);
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rtc_sleep_pu(pu_cfg);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO);
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//cancel digital PADS force no iso
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if (cfg.cpu_waiti_clk_gate) {
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CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
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} else {
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SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
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}
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/*if SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
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}
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/* force power down wifi and bt power domain */
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SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
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/* force power down bt power domain */
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SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
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}
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rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
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{
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rtc_vddsdio_config_t result;
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uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
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result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
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result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
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result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
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if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
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// Get configuration from RTC
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result.force = 1;
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result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
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result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
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return result;
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} else {
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result.force = 0;
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}
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// Otherwise, VDD_SDIO is controlled by bootstrapping pin
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uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
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result.force = 0;
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result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
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result.enable = 1;
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return result;
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}
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void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
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{
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uint32_t val = 0;
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val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
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val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
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val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
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val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
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val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
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val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
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val |= RTC_CNTL_SDIO_PD_EN;
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REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
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}
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static void set_ocode_by_efuse(int calib_version)
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{
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assert(calib_version == 1);
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// use efuse ocode.
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uint32_t ocode;
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8);
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assert(err == ESP_OK);
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(void) err;
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
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}
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static void calibrate_ocode(void)
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{
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/*
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Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL).
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Method:
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1. read current cpu config, save in old_config;
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2. switch cpu to xtal because PLL will be closed when o-code calibration;
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3. begin o-code calibration;
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4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
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5. set cpu to old-config.
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*/
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soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
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rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
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if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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cal_clk = RTC_CAL_32K_XTAL;
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} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
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cal_clk = RTC_CAL_8MD256;
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}
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uint64_t max_delay_time_us = 10000;
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uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
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uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
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uint64_t cycle0 = rtc_time_get();
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uint64_t timeout_cycle = cycle0 + max_delay_cycle;
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uint64_t cycle1 = 0;
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rtc_cpu_freq_config_t old_config;
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rtc_clk_cpu_freq_get_config(&old_config);
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rtc_clk_cpu_freq_set_xtal();
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
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bool odone_flag = 0;
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bool bg_odone_flag = 0;
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while (1) {
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odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG);
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bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
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cycle1 = rtc_time_get();
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if (odone_flag && bg_odone_flag) {
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break;
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}
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if (cycle1 >= timeout_cycle) {
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ESP_HW_LOGW(TAG, "o_code calibration fail\n");
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break;
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}
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}
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rtc_clk_cpu_freq_set_config(&old_config);
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}
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static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version)
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{
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assert(chip_version >= 3);
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uint32_t dig_dbias = 28;
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5);
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if (err != ESP_OK) {
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dig_dbias = 28;
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ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias);
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}
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return dig_dbias;
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}
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uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias)
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{
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assert(chip_version >= 3);
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uint32_t rtc_dbias = 0;
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signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0;
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esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7);
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esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7);
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esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8);
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esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8);
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if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) {
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k_rtc_ldo = 0;
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k_dig_ldo = 0;
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v_rtc_bias20 = 0;
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v_dig_bias20 = 0;
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ESP_HW_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20);
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}
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k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo;
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k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
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v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
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v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
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uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
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uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
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signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
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signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
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uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
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uint32_t v_rtc_nearest_1v15_mul10000 = 0;
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for (rtc_dbias = 15; rtc_dbias < 31; rtc_dbias++) {
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v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
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if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250)
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break;
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}
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return rtc_dbias;
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}
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static void set_rtc_dig_dbias()
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{
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/*
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1. a reasonable dig_dbias which by scaning pvt to make 160 CPU run successful stored in efuse;
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2. also we store some value in efuse, include:
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k_rtc_ldo (slope of rtc voltage & rtc_dbias);
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k_dig_ldo (slope of digital voltage & digital_dbias);
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v_rtc_bias20 (rtc voltage when rtc dbais is 20);
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v_dig_bias20 (digital voltage when digital dbais is 20).
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3. a reasonable rtc_dbias can be calculated by a certion formula.
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*/
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uint32_t rtc_dbias = 28, dig_dbias = 28;
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uint8_t chip_version = efuse_hal_get_minor_chip_version();
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if (chip_version >= 3) {
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dig_dbias = get_dig_dbias_by_efuse(chip_version);
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if (dig_dbias != 0) {
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if (dig_dbias + 4 > 28) {
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dig_dbias = 28;
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} else {
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dig_dbias += 4;
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}
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rtc_dbias = get_rtc_dbias_by_efuse(chip_version, dig_dbias); // already burn dig_dbias in efuse
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} else {
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dig_dbias = 28;
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ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in chip version: 0%d\n", chip_version);
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}
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}
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else {
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ESP_HW_LOGD(TAG, "chip_version is less than 3, not burn core voltage in efuse\n");
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}
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias);
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}
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