kopia lustrzana https://github.com/espressif/esp-idf
124 wiersze
3.2 KiB
C
124 wiersze
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <assert.h>
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#include "esp_attr.h"
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#include "soc/interrupt_reg.h"
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#include "soc/soc_caps.h"
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#include "riscv/csr.h"
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#include "sdkconfig.h"
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#if SOC_INT_PLIC_SUPPORTED
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Set global masking level. On the PLIC, all interrupt priority levels strictly less than the threshold
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* level are masked.
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*/
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#define RVHAL_INTR_ENABLE_THRESH 1
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/**
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* @brief Bitmask to enable the vector mode when writing MTVEC CSR.
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* Setting mode field to 1 treats `MTVEC` as a vector base address.
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*/
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#define MTVEC_MODE_CSR 1
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/**
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* In the case of PLIC, all the interrupt lines are dedicated to external peripherals, so the offset is 0
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*/
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#define RV_EXTERNAL_INT_COUNT 32
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#define RV_EXTERNAL_INT_OFFSET 0
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FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)
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{
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assert(rv_int_num != 0 && "Invalid CPU interrupt number");
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}
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/**
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* @brief Get the enabled interrupts on the current CPU.
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*
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* @return Bit mask of the enabled interrupts
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*/
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FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
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{
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return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
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}
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/**
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* @brief Acknowledge an edge interrupt
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*
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* @param intr_num Interrupt number (from 0 to 31)
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*/
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FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(uint32_t intr_num)
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{
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REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
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}
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/**
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* @brief Restore the CPU interrupt level to the value returned by `rv_utils_set_intlevel_regval`.
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*
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* @param restoreval Former raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
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*/
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FORCE_INLINE_ATTR void rv_utils_restore_intlevel_regval(uint32_t restoreval)
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{
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REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, restoreval);
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}
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/**
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* @brief Set the interrupt threshold to `intlevel` while getting the current level.
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*
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* @param intlevel New raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
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*
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* @return Current raw interrupt level, can be restored by calling `rv_utils_restore_intlevel_regval`.
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*/
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FORCE_INLINE_ATTR uint32_t rv_utils_set_intlevel_regval(uint32_t intlevel)
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{
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#if CONFIG_SECURE_ENABLE_TEE
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unsigned prv_mode = RV_READ_CSR(CSR_PRV_MODE);
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unsigned old_xstatus;
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if (prv_mode == PRV_M) {
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old_xstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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} else {
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old_xstatus = RV_CLEAR_CSR(ustatus, USTATUS_UIE);
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}
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uint32_t old_thresh = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
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rv_utils_restore_intlevel_regval(intlevel);
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if (prv_mode == PRV_M) {
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RV_SET_CSR(mstatus, old_xstatus & MSTATUS_MIE);
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} else {
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RV_SET_CSR(ustatus, old_xstatus & USTATUS_UIE);
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}
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return old_thresh;
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#else
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uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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uint32_t old_thresh = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
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rv_utils_restore_intlevel_regval(intlevel);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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return old_thresh;
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#endif
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* SOC_INT_PLIC_SUPPORTED */
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