kopia lustrzana https://github.com/espressif/esp-idf
88 wiersze
2.8 KiB
C
88 wiersze
2.8 KiB
C
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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/**
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* @file regi2c_saradc.h
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* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
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*
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* This file lists register fields of SAR, located on an internal configuration
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* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
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* function in adc_ll.h.
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*/
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#define I2C_SAR_ADC 0X69
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#define I2C_SAR_ADC_HOSTID 0
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#define ADC_SAR1_ENCAL_GND_ADDR 0x7
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#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
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#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
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#define ADC_SAR2_ENCAL_GND_ADDR 0x7
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#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
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#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_SAR1_DREF_ADDR 0x2
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#define ADC_SAR1_DREF_ADDR_MSB 0x6
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#define ADC_SAR1_DREF_ADDR_LSB 0x4
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#define ADC_SAR2_DREF_ADDR 0x5
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#define ADC_SAR2_DREF_ADDR_MSB 0x6
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#define ADC_SAR2_DREF_ADDR_LSB 0x4
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
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#define ADC_SARADC_DTEST_RTC_ADDR 0x7
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#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
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#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
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#define ADC_SARADC_ENT_TSENS_ADDR 0x7
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#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
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#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
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#define ADC_SARADC_ENT_RTC_ADDR 0x7
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#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
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#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
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#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
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#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
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#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
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#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
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#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
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#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
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#define I2C_SARADC_TSENS_DAC 0x6
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#define I2C_SARADC_TSENS_DAC_MSB 3
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#define I2C_SARADC_TSENS_DAC_LSB 0
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