kopia lustrzana https://github.com/espressif/esp-idf
107 wiersze
3.9 KiB
C
107 wiersze
3.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "esp_err.h"
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#include "hal/uart_types.h"
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#include "hal/gpio_types.h"
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/**
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* Default LP_IO Mux pins for LP UART
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*/
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#if CONFIG_IDF_TARGET_ESP32P4
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#define LP_UART_DEFAULT_TX_GPIO_NUM GPIO_NUM_14
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#define LP_UART_DEFAULT_RX_GPIO_NUM GPIO_NUM_15
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#define LP_UART_DEFAULT_RTS_GPIO_NUM (-1)
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#define LP_UART_DEFAULT_CTS_GPIO_NUM (-1)
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#elif CONFIG_IDF_TARGET_ESP32C6
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#define LP_UART_DEFAULT_TX_GPIO_NUM GPIO_NUM_5
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#define LP_UART_DEFAULT_RX_GPIO_NUM GPIO_NUM_4
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#define LP_UART_DEFAULT_RTS_GPIO_NUM GPIO_NUM_2
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#define LP_UART_DEFAULT_CTS_GPIO_NUM GPIO_NUM_3
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#else
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#error "LP IO Mux pins undefined for LP UART"
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#endif /* CONFIG_IDF_TARGET_ESP32P4 */
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/**
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* @brief LP UART IO pins configuration
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*/
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typedef struct {
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gpio_num_t tx_io_num; /*!< GPIO pin for UART Tx signal. Only GPIO#5 can be used as the UART Tx pin */
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gpio_num_t rx_io_num; /*!< GPIO pin for UART Rx signal. Only GPIO#4 can be used as the UART Rx pin */
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gpio_num_t rts_io_num; /*!< GPIO pin for UART RTS signal. Only GPIO#2 can be used as the UART RTS pin */
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gpio_num_t cts_io_num; /*!< GPIO pin for UART CTS signal. Only GPIO#3 can be used as the UART CTS pin */
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} lp_core_uart_pin_cfg_t;
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/**
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* @brief LP UART protocol configuration
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*/
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typedef struct {
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int baud_rate; /*!< LP UART baud rate */
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uart_word_length_t data_bits; /*!< LP UART byte size */
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uart_parity_t parity; /*!< LP UART parity mode */
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uart_stop_bits_t stop_bits; /*!< LP UART stop bits */
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uart_hw_flowcontrol_t flow_ctrl; /*!< LP UART HW flow control mode (cts/rts) */
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uint8_t rx_flow_ctrl_thresh; /*!< LP UART HW RTS threshold */
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} lp_core_uart_proto_cfg_t;
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/**
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* @brief LP UART configuration parameters
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*/
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typedef struct {
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lp_core_uart_pin_cfg_t uart_pin_cfg; /*!< LP UART pin configuration */
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lp_core_uart_proto_cfg_t uart_proto_cfg; /*!< LP UART protocol configuration */
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lp_uart_sclk_t lp_uart_source_clk; /*!< LP UART source clock selection */
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} lp_core_uart_cfg_t;
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/* Default LP UART GPIO settings */
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#define LP_UART_DEFAULT_GPIO_CONFIG() \
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.uart_pin_cfg.tx_io_num = LP_UART_DEFAULT_TX_GPIO_NUM, \
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.uart_pin_cfg.rx_io_num = LP_UART_DEFAULT_RX_GPIO_NUM, \
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.uart_pin_cfg.rts_io_num = LP_UART_DEFAULT_RTS_GPIO_NUM, \
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.uart_pin_cfg.cts_io_num = LP_UART_DEFAULT_CTS_GPIO_NUM, \
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/* Default LP UART protocol config */
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#define LP_UART_DEFAULT_PROTO_CONFIG() \
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.uart_proto_cfg.baud_rate = 115200, \
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.uart_proto_cfg.data_bits = UART_DATA_8_BITS, \
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.uart_proto_cfg.parity = UART_PARITY_DISABLE, \
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.uart_proto_cfg.stop_bits = UART_STOP_BITS_1, \
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.uart_proto_cfg.flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \
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.uart_proto_cfg.rx_flow_ctrl_thresh = 0, \
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/* Default LP UART source clock config */
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#define LP_UART_DEFAULT_CLOCK_CONFIG() \
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.lp_uart_source_clk = LP_UART_SCLK_DEFAULT, \
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/* Default LP UART GPIO settings and protocol parametes */
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#define LP_CORE_UART_DEFAULT_CONFIG() \
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{ \
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LP_UART_DEFAULT_GPIO_CONFIG() \
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LP_UART_DEFAULT_PROTO_CONFIG() \
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LP_UART_DEFAULT_CLOCK_CONFIG() \
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}
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/**
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* @brief Initialize and configure the LP UART to be used from the LP core
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*
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* @note The LP UART initialization must be called from the main core (HP CPU)
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*
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* @param cfg Configuration parameters
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* @return esp_err_t ESP_OK when successful
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*/
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esp_err_t lp_core_uart_init(const lp_core_uart_cfg_t *cfg);
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#ifdef __cplusplus
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}
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#endif
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