kopia lustrzana https://github.com/espressif/esp-idf
150 wiersze
5.3 KiB
C
150 wiersze
5.3 KiB
C
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_system.h"
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#include "esp_private/system_internal.h"
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#include "esp_attr.h"
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#include "esp_efuse.h"
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#include "esp_log.h"
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#include "riscv/riscv_interrupts.h"
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#include "riscv/interrupt.h"
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#include "esp_rom_uart.h"
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#include "soc/gpio_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timer_group_reg.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "soc/rtc_periph.h"
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#include "soc/syscon_reg.h"
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#include "soc/system_reg.h"
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#include "soc/uart_reg.h"
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#include "hal/wdt_hal.h"
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#include "cache_err_int.h"
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#include "esp32c3/rom/cache.h"
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#include "esp32c3/rom/rtc.h"
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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* core are already stopped. Stalls other core, resets hardware,
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* triggers restart.
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*/
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void IRAM_ATTR esp_restart_noos(void)
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{
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// Disable interrupts
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riscv_global_interrupts_disable();
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// Enable RTC watchdog for 1 second
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wdt_hal_context_t rtc_wdt_ctx;
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
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wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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// Reset and stall the other CPU.
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// CPU must be reset before stalling, in case it was running a s32c1i
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// instruction. This would cause memory pool to be locked by arbiter
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// to the stalled CPU, preventing current CPU from accessing this pool.
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const uint32_t core_id = cpu_hal_get_core_id();
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#if !CONFIG_FREERTOS_UNICORE
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const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
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esp_cpu_reset(other_core_id);
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esp_cpu_stall(other_core_id);
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#endif
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// Disable TG0/TG1 watchdogs
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_disable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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// Flush any data left in UART FIFOs
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esp_rom_uart_tx_wait_idle(0);
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esp_rom_uart_tx_wait_idle(1);
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// Disable cache
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Cache_Disable_ICache();
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// 2nd stage bootloader reconfigures SPI flash signals.
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// Reset them to the defaults expected by ROM.
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
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SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
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SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST |
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SYSTEM_BT_RST | SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST |
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SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
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SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | BLE_REG_REST_BIT
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|BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
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REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
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// Reset uart0 core first, then reset apb side.
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// rom will clear this bit, as well as SYSTEM_UART_RST
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SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
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// Reset timer/spi/uart
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
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SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
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// Reset dma
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
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// Set CPU back to XTAL source, no PLL, same as hard reset
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#if !CONFIG_IDF_ENV_FPGA
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rtc_clk_cpu_freq_set_xtal();
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#endif
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#if !CONFIG_FREERTOS_UNICORE
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// Clear entry point for APP CPU
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REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
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#endif
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// Reset CPUs
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if (core_id == 0) {
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// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
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#if !CONFIG_FREERTOS_UNICORE
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esp_cpu_reset(1);
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#endif
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esp_cpu_reset(0);
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}
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#if !CONFIG_FREERTOS_UNICORE
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else {
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// Running on APP CPU: need to reset PRO CPU and unstall it,
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// then reset APP CPU
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esp_cpu_reset(0);
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esp_cpu_unstall(0);
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esp_cpu_reset(1);
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}
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#endif
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while (true) {
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;
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}
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}
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