kopia lustrzana https://github.com/espressif/esp-idf
![]() Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection. |
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.. | ||
CMakeLists.txt | ||
component.mk | ||
test_float_in_isr.c | ||
test_freertos_backported_functions.c | ||
test_freertos_debug_functions.c | ||
test_freertos_eventgroups.c | ||
test_freertos_get_state.c | ||
test_freertos_isinisrcontext.c | ||
test_freertos_mutex.c | ||
test_freertos_scheduling_time.c | ||
test_freertos_task_delay_until.c | ||
test_freertos_task_delete.c | ||
test_freertos_task_notify.c | ||
test_freertos_trace_utilities.c | ||
test_isr_latency.c | ||
test_newlib_reent.c | ||
test_panic.c | ||
test_preemption.c | ||
test_queuesets.c | ||
test_spinlocks.c | ||
test_suspend_scheduler.c | ||
test_task_priorities.c | ||
test_task_suspend_resume.c | ||
test_tasks_snapshot.c | ||
test_thread_local.c | ||
test_timers.c | ||
test_xtensa_loadstore_handler.c |