kopia lustrzana https://github.com/espressif/esp-idf
7b5bdcf077
The coprocessor cpu trap signal doesnt have a stable reset value, force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU |
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|---|---|---|
| .. | ||
| include | ||
| shared/include | ||
| ulp_core | ||
| ulp_riscv.c | ||
| ulp_riscv_i2c.c | ||
| ulp_riscv_lock.c | ||