kopia lustrzana https://github.com/espressif/esp-idf
87 wiersze
2.8 KiB
C
87 wiersze
2.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include "esp_err.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* This header file contains declarations of cache manipulation functions
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* used both in flash_ops.c and flash_mmap.c.
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*
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* These functions are considered internal and are not designed to be called from applications.
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*/
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// Init mutex protecting access to spi_flash_* APIs
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void spi_flash_init_lock(void);
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// Take mutex protecting access to spi_flash_* APIs
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void spi_flash_op_lock(void);
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// Release said mutex
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void spi_flash_op_unlock(void);
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// Suspend the scheduler on both CPUs, disable cache.
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// Contrary to its name this doesn't do anything with interrupts, yet.
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// Interrupt disabling capability will be added once we implement
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// interrupt allocation API.
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void spi_flash_disable_interrupts_caches_and_other_cpu(void);
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// Enable cache, enable interrupts (to be added in future), resume scheduler
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void spi_flash_enable_interrupts_caches_and_other_cpu(void);
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// Disables non-IRAM interrupt handlers on current CPU and caches on both CPUs.
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// This function is implied to be called when other CPU is not running or running code from IRAM.
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void spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void);
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// Enable cache, enable interrupts on current CPU.
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// This function is implied to be called when other CPU is not running or running code from IRAM.
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void spi_flash_enable_interrupts_caches_no_os(void);
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// Mark the pages containing a flash region as having been
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// erased or written to. This means the flash cache needs
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// to be evicted before these pages can be flash_mmap()ed again,
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// as they may contain stale data
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//
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// Only call this while holding spi_flash_op_lock()
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// Returns true if cache was flushed, false otherwise
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bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length);
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//config cache mode
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#if !CONFIG_IDF_TARGET_ESP32
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//config instrcutin cache size and cache block size by menuconfig
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void esp_config_instruction_cache_mode(void);
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//config data cache size and cache block size by menuconfig
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void esp_config_data_cache_mode(void);
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//enable cache wrap mode for instruction cache and data cache
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esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable);
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#endif
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/** @brief Check at runtime if flash cache is enabled on both CPUs
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*
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* @return true if both CPUs have flash cache enabled, false otherwise.
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*/
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bool spi_flash_cache_enabled(void);
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/**
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* @brief Re-enable cache for the core defined as cpuid parameter.
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*
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* @param cpuid the core number to enable instruction cache for
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*/
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void spi_flash_enable_cache(uint32_t cpuid);
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#ifdef __cplusplus
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}
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#endif
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