kopia lustrzana https://github.com/espressif/esp-idf
221 wiersze
7.0 KiB
C
221 wiersze
7.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_private/esp_clk.h"
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#include "ulp_riscv.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "hal/misc.h"
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#include "ulp_common.h"
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#include "esp_rom_sys.h"
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#include "esp_check.h"
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#include "esp_private/rtc_ctrl.h"
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__attribute__((unused)) static const char* TAG = "ulp-riscv";
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esp_err_t ulp_riscv_isr_register(intr_handler_t fn, void *arg, uint32_t mask)
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{
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/* Verify that the ISR callback is valid */
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ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, "ULP RISC-V ISR is NULL");
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/* Verify that the interrupt bits are valid */
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if (!(mask & (RTC_CNTL_COCPU_INT_ST_M | RTC_CNTL_COCPU_TRAP_INT_ST_M))) {
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ESP_LOGE(TAG, "Invalid bitmask for ULP RISC-V interrupts");
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return ESP_ERR_INVALID_ARG;
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}
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/* Make sure we enable only the ULP interrupt bits.
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* We don't want other RTC interrupts triggering this ISR.
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*/
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mask &= (RTC_CNTL_COCPU_INT_ST_M | RTC_CNTL_COCPU_TRAP_INT_ST_M);
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/* Register the RTC ISR */
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ESP_RETURN_ON_ERROR(rtc_isr_register(fn, arg, mask, 0), TAG, "rtc_isr_register() failed");
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/* Enable the interrupt bits */
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SET_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, mask);
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return ESP_OK;
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}
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esp_err_t ulp_riscv_isr_deregister(intr_handler_t fn, void *arg, uint32_t mask)
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{
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/* Verify that the ISR callback is valid */
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ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, "ULP RISC-V ISR is NULL");
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/* Verify that the interrupt bits are valid */
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if (!(mask & (RTC_CNTL_COCPU_INT_ST_M | RTC_CNTL_COCPU_TRAP_INT_ST_M))) {
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ESP_LOGE(TAG, "Invalid bitmask for ULP RISC-V interrupts");
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return ESP_ERR_INVALID_ARG;
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}
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/* Make sure we disable only the ULP interrupt bits */
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mask &= (RTC_CNTL_COCPU_INT_ST_M | RTC_CNTL_COCPU_TRAP_INT_ST_M);
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/* Disable the interrupt bits */
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CLEAR_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, mask);
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/* Deregister the RTC ISR */
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ESP_RETURN_ON_ERROR(rtc_isr_deregister(fn, arg), TAG, "rtc_isr_deregister() failed");
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return ESP_OK;
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}
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static esp_err_t ulp_riscv_config_wakeup_source(ulp_riscv_wakeup_source_t wakeup_source)
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{
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esp_err_t ret = ESP_OK;
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switch (wakeup_source) {
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case ULP_RISCV_WAKEUP_SOURCE_TIMER:
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/* start ULP_TIMER */
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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break;
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case ULP_RISCV_WAKEUP_SOURCE_GPIO:
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA);
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break;
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default:
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ret = ESP_ERR_INVALID_ARG;
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}
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return ret;
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}
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esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
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{
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esp_err_t ret = ESP_OK;
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#if CONFIG_IDF_TARGET_ESP32S2
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/* Reset COCPU when power on. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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/* The coprocessor cpu trap signal doesnt have a stable reset value,
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force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
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/* Disable ULP timer */
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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/* wait for at least 1 RTC_SLOW_CLK cycle */
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esp_rom_delay_us(20);
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/* Select RISC-V as the ULP_TIMER trigger target. */
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
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/* Select ULP-RISC-V to send the DONE signal. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
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ret = ulp_riscv_config_wakeup_source(cfg->wakeup_source);
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#elif CONFIG_IDF_TARGET_ESP32S3
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/* Reset COCPU when power on. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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/* The coprocessor cpu trap signal doesnt have a stable reset value,
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force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
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/* Disable ULP timer */
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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/* wait for at least 1 RTC_SLOW_CLK cycle */
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esp_rom_delay_us(20);
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/* We do not select RISC-V as the Coprocessor here as this could lead to a hang
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* in the main CPU. Instead, we reset RTC_CNTL_COCPU_SEL after we have enabled the ULP timer.
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*
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* IDF-4510
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*/
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//CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
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/* Select ULP-RISC-V to send the DONE signal */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
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/* Set the CLKGATE_EN signal */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLKGATE_EN);
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ret = ulp_riscv_config_wakeup_source(cfg->wakeup_source);
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/* Select RISC-V as the ULP_TIMER trigger target
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* Selecting the RISC-V as the Coprocessor at the end is a workaround
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* for the hang issue recorded in IDF-4510.
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*/
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
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/* Clear any spurious wakeup trigger interrupts upon ULP startup */
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esp_rom_delay_us(20);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR | RTC_CNTL_COCPU_TRAP_INT_CLR | RTC_CNTL_ULP_CP_INT_CLR);
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#endif
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return ret;
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}
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esp_err_t ulp_riscv_run(void)
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{
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ulp_riscv_cfg_t cfg = ULP_RISCV_DEFAULT_CONFIG();
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return ulp_riscv_config_and_run(&cfg);
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}
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void ulp_riscv_timer_stop(void)
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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}
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void ulp_riscv_timer_resume(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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}
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void ulp_riscv_halt(void)
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{
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ulp_riscv_timer_stop();
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/* suspends the ulp operation*/
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
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/* Resets the processor */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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}
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void ulp_riscv_reset()
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT | RTC_CNTL_COCPU_DONE);
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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esp_rom_delay_us(20);
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT | RTC_CNTL_COCPU_DONE);
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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}
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esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes)
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{
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if (program_binary == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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if (program_size_bytes > CONFIG_ULP_COPROC_RESERVE_MEM) {
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return ESP_ERR_INVALID_SIZE;
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}
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uint8_t* base = (uint8_t*) RTC_SLOW_MEM;
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//Start by clearing memory reserved with zeros, this will also will initialize the bss:
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hal_memset(base, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
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hal_memcpy(base, program_binary, program_size_bytes);
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return ESP_OK;
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}
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