kopia lustrzana https://github.com/espressif/esp-idf
505 wiersze
16 KiB
C
505 wiersze
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <string.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_system.h"
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#include "esp_log.h"
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#include "esp_ota_ops.h"
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#include "hal/wdt_hal.h"
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#include "hal/uart_types.h"
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#include "hal/uart_ll.h"
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#include "esp_system.h"
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#include "esp_log.h"
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#include "esp_heap_caps_init.h"
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#include "esp_spi_flash.h"
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#include "esp_flash_internal.h"
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#include "esp_newlib.h"
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#include "esp_vfs_dev.h"
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#include "esp_timer.h"
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#include "esp_efuse.h"
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#include "esp_flash_encrypt.h"
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#include "esp_secure_boot.h"
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#include "esp_sleep.h"
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#include "esp_xt_wdt.h"
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/***********************************************/
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// Headers for other components init functions
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#include "nvs_flash.h"
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#include "esp_phy_init.h"
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#include "esp_coexist_internal.h"
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#if CONFIG_ESP_COREDUMP_ENABLE
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#include "esp_core_dump.h"
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#endif
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#include "esp_app_trace.h"
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#include "esp_private/dbg_stubs.h"
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#include "esp_pm.h"
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#include "esp_private/pm_impl.h"
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#include "esp_pthread.h"
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#include "esp_vfs_console.h"
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#include "brownout.h"
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#include "esp_rom_caps.h"
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#include "esp_rom_sys.h"
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// [refactor-todo] make this file completely target-independent
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/clk.h"
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#include "esp32/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/clk.h"
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#include "esp32s2/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/clk.h"
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#include "esp32s3/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/clk.h"
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#endif
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/***********************************************/
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#include "esp_private/startup_internal.h"
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// Ensure that system configuration matches the underlying number of cores.
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// This should enable us to avoid checking for both everytime.
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#if !(SOC_CPU_CORES_NUM > 1) && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#error "System has been configured to run on multiple cores, but target SoC only has a single core."
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#endif
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// Set efuse ROM_LOG_MODE on first boot
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//
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// For CONFIG_BOOT_ROM_LOG_ALWAYS_ON (default) or undefined (ESP32), leave
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// ROM_LOG_MODE undefined (no need to call this function during startup)
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#if CONFIG_BOOT_ROM_LOG_ALWAYS_OFF
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#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ALWAYS_OFF
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#elif CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW
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#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_LOW
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#elif CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH
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#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_HIGH
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#endif
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uint64_t g_startup_time = 0;
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#if SOC_APB_BACKUP_DMA
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// APB DMA lock initialising API
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extern void esp_apb_backup_dma_lock_init(void);
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#endif
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// App entry point for core 0
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extern void esp_startup_start_app(void);
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// Entry point for core 0 from hardware init (port layer)
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void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// Entry point for core [1..X] from hardware init (port layer)
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void start_cpu_other_cores(void) __attribute__((weak, alias("start_cpu_other_cores_default"))) __attribute__((noreturn));
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// App entry point for core [1..X]
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void esp_startup_start_app_other_cores(void) __attribute__((weak, alias("esp_startup_start_app_other_cores_default"))) __attribute__((noreturn));
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static volatile bool s_system_inited[SOC_CPU_CORES_NUM] = { false };
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const sys_startup_fn_t g_startup_fn[SOC_CPU_CORES_NUM] = { [0] = start_cpu0,
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#if SOC_CPU_CORES_NUM > 1
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[1 ... SOC_CPU_CORES_NUM - 1] = start_cpu_other_cores
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#endif
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};
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static volatile bool s_system_full_inited = false;
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#else
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const sys_startup_fn_t g_startup_fn[1] = { start_cpu0 };
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#endif
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#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
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// workaround for C++ exception crashes
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void _Unwind_SetNoFunctionContextInstall(unsigned char enable) __attribute__((weak, alias("_Unwind_SetNoFunctionContextInstall_Default")));
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// workaround for C++ exception large memory allocation
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void _Unwind_SetEnableExceptionFdeSorting(unsigned char enable);
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static IRAM_ATTR void _Unwind_SetNoFunctionContextInstall_Default(unsigned char enable __attribute__((unused)))
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{
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(void)0;
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}
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#endif // CONFIG_COMPILER_CXX_EXCEPTIONS
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static const char* TAG = "cpu_start";
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/**
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* This function overwrites a the same function of libsupc++ (part of libstdc++).
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* Consequently, libsupc++ will then follow our configured exception emergency pool size.
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*
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* It will be called even with -fno-exception for user code since the stdlib still uses exceptions.
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*/
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size_t __cxx_eh_arena_size_get(void)
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{
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#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
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return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE;
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#else
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return 0;
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#endif
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}
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/**
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* Xtensa gcc is configured to emit a .ctors section, RISC-V gcc is configured with --enable-initfini-array
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* so it emits an .init_array section instead.
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* But the init_priority sections will be sorted for iteration in ascending order during startup.
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* The rest of the init_array sections is sorted for iteration in descending order during startup, however.
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* Hence a different section is generated for the init_priority functions which is looped
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* over in ascending direction instead of descending direction.
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* The RISC-V-specific behavior is dependent on the linker script ld/esp32c3/sections.ld.in.
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*/
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static void do_global_ctors(void)
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{
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#if __riscv
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extern void (*__init_priority_array_start)(void);
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extern void (*__init_priority_array_end)(void);
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#endif
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extern void (*__init_array_start)(void);
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extern void (*__init_array_end)(void);
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#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
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struct object { long placeholder[ 10 ]; };
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void __register_frame_info (const void *begin, struct object *ob);
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extern char __eh_frame[];
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static struct object ob;
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__register_frame_info( __eh_frame, &ob );
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#endif // CONFIG_COMPILER_CXX_EXCEPTIONS
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void (**p)(void);
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#if __riscv
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for (p = &__init_priority_array_start; p < &__init_priority_array_end; ++p) {
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ESP_EARLY_LOGD(TAG, "calling init function: %p", *p);
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(*p)();
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}
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#endif
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for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
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ESP_EARLY_LOGD(TAG, "calling init function: %p", *p);
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(*p)();
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}
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}
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static void do_system_init_fn(void)
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{
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extern esp_system_init_fn_t _esp_system_init_fn_array_start;
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extern esp_system_init_fn_t _esp_system_init_fn_array_end;
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esp_system_init_fn_t *p;
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for (p = &_esp_system_init_fn_array_end - 1; p >= &_esp_system_init_fn_array_start; --p) {
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if (p->cores & BIT(cpu_hal_get_core_id())) {
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(*(p->fn))();
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}
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}
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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s_system_inited[cpu_hal_get_core_id()] = true;
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#endif
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}
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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static void esp_startup_start_app_other_cores_default(void)
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{
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while (1) {
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esp_rom_delay_us(UINT32_MAX);
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}
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}
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static void IRAM_ATTR start_cpu_other_cores_default(void)
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{
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do_system_init_fn();
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while (!s_system_full_inited) {
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esp_rom_delay_us(100);
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}
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esp_startup_start_app_other_cores();
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}
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#endif
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static void do_core_init(void)
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{
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/* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
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If the heap allocator is initialized first, it will put free memory linked list items into
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memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
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corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
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works around this problem.
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With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the
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app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may
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fail initializing it properly. */
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heap_caps_init();
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// When apptrace module is enabled, there will be SEGGER_SYSVIEW calls in the newlib init.
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// SEGGER_SYSVIEW relies on apptrace module
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// apptrace module uses esp_timer_get_time to determine timeout conditions.
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// esp_timer early initialization is required for esp_timer_get_time to work.
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esp_timer_early_init();
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esp_newlib_init();
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if (g_spiram_ok) {
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#if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
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esp_err_t r=esp_spiram_add_to_heapalloc();
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if (r != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
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abort();
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}
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#if CONFIG_SPIRAM_USE_MALLOC
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heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
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#endif
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#endif
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}
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#if CONFIG_ESP32_BROWNOUT_DET || \
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CONFIG_ESP32S2_BROWNOUT_DET || \
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CONFIG_ESP32S3_BROWNOUT_DET || \
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CONFIG_ESP32C3_BROWNOUT_DET || \
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CONFIG_ESP32H2_BROWNOUT_DET
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// [refactor-todo] leads to call chain rtc_is_register (driver) -> esp_intr_alloc (esp32/esp32s2) ->
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// malloc (newlib) -> heap_caps_malloc (heap), so heap must be at least initialized
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esp_brownout_init();
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#endif
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esp_newlib_time_init();
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#if CONFIG_VFS_SUPPORT_IO
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// VFS console register.
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esp_err_t vfs_err = esp_vfs_console_register();
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assert(vfs_err == ESP_OK && "Failed to register vfs console");
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#endif
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#if defined(CONFIG_VFS_SUPPORT_IO) && !defined(CONFIG_ESP_CONSOLE_NONE)
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const static char *default_stdio_dev = "/dev/console/";
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esp_reent_init(_GLOBAL_REENT);
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_GLOBAL_REENT->_stdin = fopen(default_stdio_dev, "r");
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_GLOBAL_REENT->_stdout = fopen(default_stdio_dev, "w");
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_GLOBAL_REENT->_stderr = fopen(default_stdio_dev, "w");
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#if ESP_ROM_NEEDS_SWSETUP_WORKAROUND
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/*
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- This workaround for printf functions using 32-bit time_t after the 64-bit time_t upgrade
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- The 32-bit time_t usage is triggered through ROM Newlib functions printf related functions calling __swsetup_r() on
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the first call to a particular file pointer (i.e., stdin, stdout, stderr)
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- Thus, we call the toolchain version of __swsetup_r() now (before any printf calls are made) to setup all of the
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file pointers. Thus, the ROM newlib code will never call the ROM version of __swsetup_r().
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- See IDFGH-7728 for more details
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*/
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extern int __swsetup_r(struct _reent *, FILE *);
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__swsetup_r(_GLOBAL_REENT, _GLOBAL_REENT->_stdout);
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__swsetup_r(_GLOBAL_REENT, _GLOBAL_REENT->_stderr);
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__swsetup_r(_GLOBAL_REENT, _GLOBAL_REENT->_stdin);
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#endif // ESP_ROM_NEEDS_SWSETUP_WORKAROUND
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#else // defined(CONFIG_VFS_SUPPORT_IO) && !defined(CONFIG_ESP_CONSOLE_NONE)
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_REENT_SMALL_CHECK_INIT(_GLOBAL_REENT);
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#endif // defined(CONFIG_VFS_SUPPORT_IO) && !defined(CONFIG_ESP_CONSOLE_NONE)
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esp_err_t err __attribute__((unused));
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err = esp_pthread_init();
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assert(err == ESP_OK && "Failed to init pthread module!");
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spi_flash_init();
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/* init default OS-aware flash access critical section */
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spi_flash_guard_set(&g_flash_guard_default_ops);
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esp_flash_app_init();
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esp_err_t flash_ret = esp_flash_init_default_chip();
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assert(flash_ret == ESP_OK);
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(void)flash_ret;
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
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#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
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const esp_partition_t *efuse_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM, NULL);
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if (efuse_partition) {
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esp_efuse_init_virtual_mode_in_flash(efuse_partition->address, efuse_partition->size);
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}
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#endif
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#endif
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#if CONFIG_SECURE_DISABLE_ROM_DL_MODE
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err = esp_efuse_disable_rom_download_mode();
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assert(err == ESP_OK && "Failed to disable ROM download mode");
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#endif
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#if CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
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err = esp_efuse_enable_rom_secure_download_mode();
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assert(err == ESP_OK && "Failed to enable Secure Download mode");
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#endif
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#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
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esp_efuse_disable_basic_rom_console();
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#endif
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#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
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esp_flash_encryption_init_checks();
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#endif
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#if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT)
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// Note: in some configs this may read flash, so placed after flash init
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esp_secure_boot_init_checks();
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#endif
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#ifdef ROM_LOG_MODE
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esp_efuse_set_rom_log_scheme(ROM_LOG_MODE);
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#endif
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#if CONFIG_ESP_XT_WDT
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esp_xt_wdt_config_t cfg = {
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.timeout = CONFIG_ESP_XT_WDT_TIMEOUT,
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.auto_backup_clk_enable = CONFIG_ESP_XT_WDT_BACKUP_CLK_ENABLE,
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};
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err = esp_xt_wdt_init(&cfg);
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assert(err == ESP_OK && "Failed to init xtwdt");
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#endif
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}
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static void do_secondary_init(void)
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{
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// The port layer transferred control to this function with other cores 'paused',
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// resume execution so that cores might execute component initialization functions.
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startup_resume_other_cores();
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#endif
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// Execute initialization functions esp_system_init_fn_t assigned to the main core. While
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// this is happening, all other cores are executing the initialization functions
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// assigned to them since they have been resumed already.
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do_system_init_fn();
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// Wait for all cores to finish secondary init.
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volatile bool system_inited = false;
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while (!system_inited) {
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system_inited = true;
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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system_inited &= s_system_inited[i];
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}
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esp_rom_delay_us(100);
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}
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#endif
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}
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static void start_cpu0_default(void)
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{
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ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
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int cpu_freq = esp_clk_cpu_freq();
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ESP_EARLY_LOGI(TAG, "cpu freq: %d", cpu_freq);
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// Display information about the current running image.
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if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) {
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const esp_app_desc_t *app_desc = esp_ota_get_app_description();
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ESP_EARLY_LOGI(TAG, "Application information:");
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#ifndef CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR
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ESP_EARLY_LOGI(TAG, "Project name: %s", app_desc->project_name);
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#endif
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#ifndef CONFIG_APP_EXCLUDE_PROJECT_VER_VAR
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ESP_EARLY_LOGI(TAG, "App version: %s", app_desc->version);
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#endif
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#ifdef CONFIG_BOOTLOADER_APP_SECURE_VERSION
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ESP_EARLY_LOGI(TAG, "Secure version: %d", app_desc->secure_version);
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#endif
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#ifdef CONFIG_APP_COMPILE_TIME_DATE
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ESP_EARLY_LOGI(TAG, "Compile time: %s %s", app_desc->date, app_desc->time);
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#endif
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char buf[17];
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esp_ota_get_app_elf_sha256(buf, sizeof(buf));
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ESP_EARLY_LOGI(TAG, "ELF file SHA256: %s...", buf);
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ESP_EARLY_LOGI(TAG, "ESP-IDF: %s", app_desc->idf_ver);
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}
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// Initialize core components and services.
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do_core_init();
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// Execute constructors.
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do_global_ctors();
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// Execute init functions of other components; blocks
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// until all cores finish (when !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE).
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do_secondary_init();
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// Now that the application is about to start, disable boot watchdog
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#ifndef CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
|
|
|
|
#if SOC_CPU_CORES_NUM > 1 && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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s_system_full_inited = true;
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|
#endif
|
|
|
|
esp_startup_start_app();
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|
while (1);
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|
}
|
|
|
|
IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
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|
{
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|
esp_timer_init();
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|
|
|
#if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND && !CONFIG_PM_SLP_DISABLE_GPIO
|
|
// Configure to isolate (disable the Input/Output/Pullup/Pulldown
|
|
// function of the pin) all GPIO pins in sleep state
|
|
esp_sleep_config_gpio_isolate();
|
|
// Enable automatic switching of GPIO configuration
|
|
esp_sleep_enable_gpio_switch(true);
|
|
#endif
|
|
|
|
#if CONFIG_APPTRACE_ENABLE
|
|
esp_err_t err = esp_apptrace_init();
|
|
assert(err == ESP_OK && "Failed to init apptrace module on PRO CPU!");
|
|
#endif
|
|
#if CONFIG_APPTRACE_SV_ENABLE
|
|
SEGGER_SYSVIEW_Conf();
|
|
#endif
|
|
|
|
#if CONFIG_ESP_DEBUG_STUBS_ENABLE
|
|
esp_dbg_stubs_init();
|
|
#endif
|
|
|
|
#if defined(CONFIG_PM_ENABLE)
|
|
esp_pm_impl_init();
|
|
#endif
|
|
|
|
#if CONFIG_ESP_COREDUMP_ENABLE
|
|
esp_core_dump_init();
|
|
#endif
|
|
|
|
#if SOC_APB_BACKUP_DMA
|
|
esp_apb_backup_dma_lock_init();
|
|
#endif
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
|
esp_coex_adapter_register(&g_coex_adapter_funcs);
|
|
coex_pre_init();
|
|
#endif
|
|
|
|
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
|
|
ESP_EARLY_LOGD(TAG, "Setting C++ exception workarounds.");
|
|
_Unwind_SetNoFunctionContextInstall(1);
|
|
_Unwind_SetEnableExceptionFdeSorting(0);
|
|
#endif // CONFIG_COMPILER_CXX_EXCEPTIONS
|
|
}
|