esp-idf/components/soc/esp32c3
Omar Chebib 752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
2022-06-16 11:53:39 +08:00
..
include/soc Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' 2022-06-16 11:53:39 +08:00
ld
CMakeLists.txt
adc_periph.c
dedic_gpio_periph.c
gdma_periph.c
gpio_periph.c
i2c_bbpll.h
i2c_periph.c
i2s_periph.c
interrupts.c
ledc_periph.c
rmt_periph.c
sigmadelta_periph.c
spi_periph.c
timer_periph.c
uart_periph.c