kopia lustrzana https://github.com/espressif/esp-idf
554 wiersze
17 KiB
C
554 wiersze
17 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdlib.h>
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#include "esp_attr.h"
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#include "soc/adc_periph.h"
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#include "soc/apb_saradc_struct.h"
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#include "soc/apb_saradc_reg.h"
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#include "soc/rtc_cntl_struct.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/clk_tree_defs.h"
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#include "hal/misc.h"
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#include "hal/assert.h"
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#include "hal/adc_types.h"
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#include "hal/adc_types_private.h"
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#include "hal/regi2c_ctrl.h"
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#include "soc/regi2c_saradc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
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#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
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/*---------------------------------------------------------------
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Oneshot
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---------------------------------------------------------------*/
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#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
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#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
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/*---------------------------------------------------------------
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DMA
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---------------------------------------------------------------*/
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#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
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#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
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#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
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#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
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#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
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#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
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#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
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#define ADC_LL_CLKM_DIV_B_DEFAULT 1
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#define ADC_LL_CLKM_DIV_A_DEFAULT 0
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/*---------------------------------------------------------------
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PWDET (Power Detect)
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---------------------------------------------------------------*/
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#define ADC_LL_PWDET_CCT_DEFAULT (4)
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typedef enum {
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ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
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ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */
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ADC_LL_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */
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} adc_ll_power_t;
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typedef enum {
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ADC_LL_CTRL_DIG = 0, ///< For ADC1. Select DIG controller.
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} adc_ll_controller_t;
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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/**
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* Set adc fsm interval parameter for digital controller. These values are fixed for same platforms.
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*
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* @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor.
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* @param start_wait Delay time after open xpd.
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* @param standby_wait Delay time to close xpd.
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*/
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static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
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{
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// Internal FSM reset wait time
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HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_rstb_wait, rst_wait);
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// Internal FSM start wait time
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HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_xpd_wait, start_wait);
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// Internal FSM standby wait time
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HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_standby_wait, standby_wait);
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}
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/**
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* Set adc sample cycle for digital controller.
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*
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* @note Normally, please use default value.
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* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
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* Range: 2 ~ 0xFF.
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*/
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static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
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{
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/* Should be called before writing I2C registers. */
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SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
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}
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/**
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* Set SAR ADC module clock division factor.
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* SAR ADC clock divided from digital controller clock.
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*
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* @param div Division factor.
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*/
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static inline void adc_ll_digi_set_clk_div(uint32_t div)
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{
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/* ADC clock divided from digital controller clock clk */
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HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div);
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}
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/**
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* Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize.
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*
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* @note Only ADC2 have arbiter function.
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* @param cycle range: 0 ~ 4.
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*/
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static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
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{
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APB_SARADC.saradc_ctrl.saradc_saradc_wait_arb_cycle = cycle;
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}
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/**
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* ADC Digital controller output data invert or not.
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*
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* @param adc_n ADC unit.
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* @param inv_en data invert or not.
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*/
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static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
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{
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if (adc_n == ADC_UNIT_1) {
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APB_SARADC.saradc_ctrl2.saradc_saradc_sar1_inv = inv_en; // Enable / Disable ADC data invert
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} else { // adc_n == ADC_UNIT_2
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APB_SARADC.saradc_ctrl2.saradc_saradc_sar2_inv = inv_en; // Enable / Disable ADC data invert
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}
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}
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/**
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* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
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* Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1).
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*
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* @param div_num Division factor. Range: 0 ~ 255.
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* @param div_b Division factor. Range: 1 ~ 63.
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* @param div_a Division factor. Range: 0 ~ 63.
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*/
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static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_apb_adc_clkm_conf, saradc_reg_clkm_div_num, div_num);
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APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clkm_div_b = div_b;
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APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clkm_div_a = div_a;
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}
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/**
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* Enable clock and select clock source for ADC digital controller.
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*
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* @param clk_src clock source for ADC digital controller.
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*/
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static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
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{
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APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clk_sel = 2;
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
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}
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/**
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* Disable clock for ADC digital controller.
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*/
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static inline void adc_ll_digi_controller_clk_disable(void)
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{
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0;
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}
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/**
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* Reset adc digital controller filter.
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*
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* @param idx Filter index
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* @param adc_n ADC unit.
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*/
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static inline void adc_ll_digi_filter_reset(adc_digi_iir_filter_t idx, adc_unit_t adc_n)
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{
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(void)adc_n;
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APB_SARADC.saradc_filter_ctrl0.saradc_filter_reset = 1;
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APB_SARADC.saradc_filter_ctrl0.saradc_filter_reset = 0;
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}
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/**
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* Set adc digital controller filter coeff.
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*
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* @param idx filter index
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* @param adc_n adc unit
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* @param channel adc channel
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* @param coeff filter coeff
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*/
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static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_unit_t adc_n, adc_channel_t channel, adc_digi_iir_filter_coeff_t coeff)
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{
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uint32_t factor_reg_val = 0;
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switch (coeff) {
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case ADC_DIGI_IIR_FILTER_COEFF_2:
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factor_reg_val = 1;
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break;
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case ADC_DIGI_IIR_FILTER_COEFF_4:
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factor_reg_val = 2;
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break;
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case ADC_DIGI_IIR_FILTER_COEFF_8:
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factor_reg_val = 3;
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break;
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case ADC_DIGI_IIR_FILTER_COEFF_16:
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factor_reg_val = 4;
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break;
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case ADC_DIGI_IIR_FILTER_COEFF_64:
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factor_reg_val = 6;
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break;
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default:
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HAL_ASSERT(false);
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}
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if (idx == ADC_DIGI_IIR_FILTER_0) {
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APB_SARADC.saradc_filter_ctrl0.saradc_filter_channel0 = ((adc_n + 1) << 3) | (channel & 0x7);
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APB_SARADC.saradc_filter_ctrl1.saradc_filter_factor0 = factor_reg_val;
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} else if (idx == ADC_DIGI_IIR_FILTER_1) {
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APB_SARADC.saradc_filter_ctrl0.saradc_filter_channel1 = ((adc_n + 1) << 3) | (channel & 0x7);
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APB_SARADC.saradc_filter_ctrl1.saradc_filter_factor1 = factor_reg_val;
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}
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}
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/**
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* Enable adc digital controller filter.
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* Filtering the ADC data to obtain smooth data at higher sampling rates.
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*
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* @param idx filter index
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* @param adc_n ADC unit
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* @param enable Enable / Disable
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*/
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static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit_t adc_n, bool enable)
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{
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(void)adc_n;
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if (!enable) {
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if (idx == ADC_DIGI_IIR_FILTER_0) {
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APB_SARADC.saradc_filter_ctrl0.saradc_filter_channel0 = 0xF;
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APB_SARADC.saradc_filter_ctrl1.saradc_filter_factor0 = 0;
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} else if (idx == ADC_DIGI_IIR_FILTER_1) {
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APB_SARADC.saradc_filter_ctrl0.saradc_filter_channel1 = 0xF;
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APB_SARADC.saradc_filter_ctrl1.saradc_filter_factor1 = 0;
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}
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}
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//nothing to do to enable, after adc_ll_digi_filter_set_factor, it's enabled.
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}
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/**
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* Reset adc digital controller.
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*/
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static inline void adc_ll_digi_reset(void)
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{
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APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 1;
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APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 0;
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}
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/*---------------------------------------------------------------
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PWDET(Power detect) controller setting
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---------------------------------------------------------------*/
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/**
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* Set adc cct for PWDET controller.
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*
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* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
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* @param cct Range: 0 ~ 7.
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*/
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static inline void adc_ll_pwdet_set_cct(uint32_t cct)
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{
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/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
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RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct;
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}
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/**
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* Get adc cct for PWDET controller.
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*
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* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
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* @return cct Range: 0 ~ 7.
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*/
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static inline uint32_t adc_ll_pwdet_get_cct(void)
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{
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/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
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return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
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}
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* Set ADC module power management.
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*
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* @param manage Set ADC power status.
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*/
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__attribute__((always_inline))
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static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage)
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{
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/* Bit1 0:Fsm 1: SW mode
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Bit0 0:SW mode power down 1: SW mode power on */
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if (manage == ADC_LL_POWER_SW_ON) {
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
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APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3;
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} else if (manage == ADC_LL_POWER_BY_FSM) {
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
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APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0;
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} else if (manage == ADC_LL_POWER_SW_OFF) {
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0;
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APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2;
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}
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}
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__attribute__((always_inline))
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static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
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{
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//Not used on ESP32-C2
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}
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/* ADC calibration code. */
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/**
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* @brief Set common calibration configuration. Should be shared with other parts (PWDET).
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*/
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__attribute__((always_inline))
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static inline void adc_ll_calibration_init(adc_unit_t adc_n)
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{
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(void)adc_n;
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1);
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}
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/**
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* Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration.
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*
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* @note Different ADC units and different attenuation options use different calibration data (initial data).
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*
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* @param adc_n ADC index number.
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* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
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* false: Use IO external voltage as calibration voltage.
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*/
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static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, bool internal_gnd)
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{
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(void)adc_n;
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/* Enable/disable internal connect GND (for calibration). */
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if (internal_gnd) {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
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} else {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
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}
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}
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/**
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* Resume register status after calibration.
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*
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* @param adc_n ADC index number.
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*/
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static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
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{
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(void)adc_n;
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
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}
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/**
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* Set the calibration result to ADC.
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*
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* @note Different ADC units and different attenuation options use different calibration data (initial data).
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*
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* @param adc_n ADC index number.
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*/
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__attribute__((always_inline))
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static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
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{
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(void)adc_n;
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uint8_t msb = param >> 8;
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uint8_t lsb = param & 0xFF;
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
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}
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/*---------------------------------------------------------------
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Oneshot Read
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---------------------------------------------------------------*/
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/**
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* Set adc output data format for oneshot mode
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*
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* @note ESP32C2 Oneshot mode only supports 12bit.
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* @param adc_n ADC unit.
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* @param bits Output data bits width option.
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*/
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static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits)
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{
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//ESP32C2 only supports 12bit, leave here for compatibility
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HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT);
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}
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/**
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* Enable adc channel to start convert.
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*
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* @note Only one channel can be selected for measurement.
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*
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* @param adc_n ADC unit.
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* @param channel ADC channel number for each ADCn.
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*/
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static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel)
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{
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | channel);
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}
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/**
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* Disable adc channel to start convert.
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*
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* @note Only one channel can be selected in once measurement.
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*
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* @param adc_n ADC unit.
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*/
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static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n)
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{
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF);
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}
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/**
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* Start oneshot conversion by software
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*
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* @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle,
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* otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow.
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* This hardware limitation will be removed in future versions.
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*/
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static inline void adc_oneshot_ll_start(bool val)
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{
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APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_start = val;
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}
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/**
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* Clear the event for each ADCn for Oneshot mode
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*
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* @param event ADC event
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*/
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static inline void adc_oneshot_ll_clear_event(uint32_t event_mask)
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{
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APB_SARADC.saradc_int_clr.val |= event_mask;
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}
|
|
|
|
/**
|
|
* Check the event for each ADCn for Oneshot mode
|
|
*
|
|
* @param event ADC event
|
|
*
|
|
* @return
|
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* -true : The conversion process is finish.
|
|
* -false : The conversion process is not finish.
|
|
*/
|
|
static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
|
|
{
|
|
return (APB_SARADC.saradc_int_raw.val & event_mask);
|
|
}
|
|
|
|
/**
|
|
* Get the converted value for each ADCn for RTC controller.
|
|
*
|
|
* @param adc_n ADC unit.
|
|
* @return
|
|
* - Converted value.
|
|
*/
|
|
static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
|
|
{
|
|
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
|
uint32_t ret_val = 0;
|
|
ret_val = APB_SARADC.saradc1_data_status.saradc1_data & 0xfff;
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* Analyze whether the obtained raw data is correct.
|
|
* ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
|
|
*
|
|
* @param adc_n ADC unit.
|
|
* @param raw_data ADC raw data input (convert value).
|
|
* @return
|
|
* - 1: The data is correct to use.
|
|
* - 0: The data is invalid.
|
|
*/
|
|
static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data)
|
|
{
|
|
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* ADC module RTC output data invert or not.
|
|
*
|
|
* @param adc_n ADC unit.
|
|
* @param inv_en data invert or not.
|
|
*/
|
|
static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en)
|
|
{
|
|
(void)adc_n;
|
|
(void)inv_en;
|
|
//For compatibility
|
|
}
|
|
|
|
/**
|
|
* Enable oneshot conversion trigger
|
|
*
|
|
* @param adc_n ADC unit
|
|
*/
|
|
static inline void adc_oneshot_ll_enable(adc_unit_t adc_n)
|
|
{
|
|
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
|
APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1;
|
|
}
|
|
|
|
/**
|
|
* Disable oneshot conversion trigger for all the ADC units
|
|
*/
|
|
static inline void adc_oneshot_ll_disable_all_unit(void)
|
|
{
|
|
APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0;
|
|
APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0;
|
|
}
|
|
|
|
/**
|
|
* Set attenuation
|
|
*
|
|
* @note Attenuation is for all channels
|
|
*
|
|
* @param adc_n ADC unit
|
|
* @param channel ADC channel
|
|
* @param atten ADC attenuation
|
|
*/
|
|
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
|
|
{
|
|
(void)adc_n;
|
|
(void)channel;
|
|
// Attenuation is for all channels, unit and channel are for compatibility
|
|
APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten = atten;
|
|
}
|
|
|
|
/**
|
|
* Get the attenuation of a particular channel on ADCn.
|
|
*
|
|
* @param adc_n ADC unit.
|
|
* @param channel ADCn channel number.
|
|
* @return atten The attenuation option.
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
|
|
{
|
|
(void)adc_n;
|
|
(void)channel;
|
|
return (adc_atten_t)(APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten);
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|