esp-idf/components/spi_flash/esp32s3
Armando c331c85318 mspi: make cpu clock source switch safe
For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be
cleared. When system clock switches up, the delays should be restored.
2021-10-19 21:47:27 +08:00
..
flash_ops_esp32s3.c
mspi_timing_tuning_configs.h
opi_flash_cmd_format_mxic.h
opi_flash_private.h
spi_flash_oct_flash_init.c
spi_flash_rom_patch.c
spi_timing_config.c
spi_timing_config.h