kopia lustrzana https://github.com/espressif/esp-idf
113 wiersze
3.4 KiB
C
113 wiersze
3.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/assert.h"
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#include "hal/log.h"
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static const char *CLK_HAL_TAG = "clk_hal";
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uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
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{
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switch (cpu_clk_src) {
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case SOC_CPU_CLK_SRC_XTAL:
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return clk_hal_xtal_get_freq_mhz();
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case SOC_CPU_CLK_SRC_PLL:
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return clk_ll_bbpll_get_freq_mhz();
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case SOC_CPU_CLK_SRC_RC_FAST:
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return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
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case SOC_CPU_CLK_SRC_APLL:
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return clk_hal_apll_get_freq_hz() / MHZ;
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default:
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// Unknown CPU_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_cpu_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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switch (source) {
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case SOC_CPU_CLK_SRC_PLL: {
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// PLL 320MHz, CPU 240MHz is an undetermined state
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uint32_t pll_freq_mhz = clk_ll_bbpll_get_freq_mhz();
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uint32_t cpu_freq_mhz = clk_ll_cpu_get_freq_mhz_from_pll();
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if (pll_freq_mhz == CLK_LL_PLL_320M_FREQ_MHZ && cpu_freq_mhz == CLK_LL_PLL_240M_FREQ_MHZ) {
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HAL_LOGE(CLK_HAL_TAG, "Invalid cpu config");
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return 0;
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}
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return cpu_freq_mhz * MHZ;
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}
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case SOC_CPU_CLK_SRC_APLL: {
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uint32_t apll_freq_hz = clk_hal_apll_get_freq_hz();
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uint32_t divider = clk_ll_cpu_get_divider_from_apll();
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if (divider == 0) {
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HAL_LOGE(CLK_HAL_TAG, "Invalid cpu config");
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return 0;
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}
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return apll_freq_hz / divider;
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}
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default: // SOC_CPU_CLK_SRC_XTAL, SOC_CPU_CLK_SRC_RC_FAST...
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / clk_ll_cpu_get_divider();
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}
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}
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uint32_t clk_hal_ahb_get_freq_hz(void)
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{
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// AHB_CLK path is highly dependent on CPU_CLK path
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switch (clk_ll_cpu_get_src()) {
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case SOC_CPU_CLK_SRC_PLL:
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// AHB_CLK is a fixed value when CPU_CLK is clocked from PLL
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return CLK_LL_AHB_MAX_FREQ_MHZ * MHZ;
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case SOC_CPU_CLK_SRC_APLL:
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return clk_hal_cpu_get_freq_hz() >> 1;
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default: // SOC_CPU_CLK_SRC_XTAL, SOC_CPU_CLK_SRC_RC_FAST...
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return clk_hal_cpu_get_freq_hz();
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}
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}
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uint32_t clk_hal_apb_get_freq_hz(void)
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{
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return clk_hal_ahb_get_freq_hz();
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}
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uint32_t clk_hal_lp_slow_get_freq_hz(void)
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{
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switch (clk_ll_rtc_slow_get_src()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
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return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
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return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256:
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return SOC_CLK_RC_FAST_D256_FREQ_APPROX;
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default:
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// Unknown RTC_SLOW_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_xtal_get_freq_mhz(void)
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{
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// ESP32S2's supported XTAL frequency is fixed, didn't save in the RTC storage register
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return CLK_LL_XTAL_FREQ_MHZ;
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}
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uint32_t clk_hal_apll_get_freq_hz(void)
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{
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uint32_t xtal_freq_mhz = clk_hal_xtal_get_freq_mhz();
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uint32_t o_div = 0;
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uint32_t sdm0 = 0;
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uint32_t sdm1 = 0;
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uint32_t sdm2 = 0;
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clk_ll_apll_get_config(&o_div, &sdm0, &sdm1, &sdm2);
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uint32_t apll_freq_hz = (uint32_t)(xtal_freq_mhz * MHZ * (4 + sdm2 + (float)sdm1/256.0 + (float)sdm0/65536.0) /
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(((float)o_div + 2) * 2));
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return apll_freq_hz;
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}
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