kopia lustrzana https://github.com/espressif/esp-idf
237 wiersze
10 KiB
C
237 wiersze
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/syscon_reg.h"
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#include "soc/bb_reg.h"
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#include "soc/nrx_reg.h"
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#include "soc/fe_reg.h"
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#include "soc/timer_group_reg.h"
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#include "soc/system_reg.h"
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#include "esp32c2/rom/ets_sys.h"
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#include "esp32c2/rom/rtc.h"
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#include "regi2c_ctrl.h"
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#include "soc/regi2c_lp_bias.h"
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#include "soc/regi2c_dig_reg.h"
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/**
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* Configure whether certain peripherals are powered down in deep sleep
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* @param cfg power down flags as rtc_sleep_pu_config_t structure
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*/
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void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
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{
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REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
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if (cfg.sram_fpu) {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
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} else {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
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}
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if (cfg.rom_ram_fpu) {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
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} else {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
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}
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}
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void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config)
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{
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*out_config = (rtc_sleep_config_t) {
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.lslp_mem_inf_fpu = 1,
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.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0,
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.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0,
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.wdt_flashboot_mod_en = 0,
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.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0,
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.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1,
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.deep_slp_reject = 1,
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.light_slp_reject = 1,
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};
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if (sleep_flags & RTC_SLEEP_PD_DIG) {
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assert(sleep_flags & RTC_SLEEP_PD_XTAL);
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if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)) {
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/*
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* dbg_att_slp need to set to 0: rtc voltage is about 0.98v
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* support all features:
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* - 8MD256 as RTC slow clock src
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* - RTC IO as input
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*/
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out_config->rtc_regulator_fpu = 1;
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out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP;
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out_config->rtc_dbias_slp = 0;
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} else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) {
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/*
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* Default mode
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* rtc voltage in sleep need stable and not less than 0.7v
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* support features:
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* - RTC IO as input
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*/
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out_config->rtc_regulator_fpu = 1;
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out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
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out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7;
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} else {
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/*
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* rtc regulator not opened and rtc voltage is about 0.66v (ultra low power):
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* not support features:
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* - 8MD256 as RTC slow clock src
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* - RTC IO as input
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*/
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out_config->rtc_regulator_fpu = 0;
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out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
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out_config->rtc_dbias_slp = 0;
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}
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} else {
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out_config->rtc_regulator_fpu = 1;
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// rtc & digital voltage from high to low
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if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) {
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/*
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* digital voltage need to be >= 1.1v
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* Support all features:
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* - XTAL
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* - RC 8M used by digital system
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* - 8MD256 as RTC slow clock src (only need dbg_atten_slp set to 0)
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*/
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out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
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out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10;
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out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10;
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} else if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)){
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/*
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* dbg_att_slp need to set to 0: digital voltage is about 0.64v & rtc voltage is 0.98v
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* Support features:
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* - 8MD256 as RTC slow clock src
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*/
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out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
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out_config->dig_dbias_slp = 0;
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out_config->rtc_dbias_slp = 0;
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} else {
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/*
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* digital voltage not less than 0.6v.
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* not support features:
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* - XTAL
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* - RC 8M used by digital system
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* - 8MD256 as RTC slow clock src
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*/
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out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
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out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6;
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out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6;
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}
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}
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if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) {
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out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON;
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out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON;
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} else {
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out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
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out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
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}
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}
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void rtc_sleep_init(rtc_sleep_config_t cfg)
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{
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if (cfg.lslp_mem_inf_fpu) {
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rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
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rtc_sleep_pu(pu_cfg);
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}
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assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
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if (cfg.deep_slp) {
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
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RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
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RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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}
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu);
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if (!cfg.int_8m_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
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}
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/* enable VDDSDIO control by state machine */
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REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_VDD_SPI_PWR_FORCE);
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REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_VDD_SPI_PD_EN, cfg.vddsdio_pd_en);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
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REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
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}
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void rtc_sleep_low_init(uint32_t slowclk_period)
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{
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// set 5 PWC state machine times to fit in main state machine time
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
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}
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static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
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uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
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{
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REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
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SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
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RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
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/* Start entry into sleep mode */
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
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while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
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RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
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;
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}
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return rtc_sleep_finish(lslp_mem_inf_fpu);
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}
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static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
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{
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/* In deep sleep mode, we never get here */
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uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
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SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
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RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
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/* restore config if it is a light sleep */
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if (lslp_mem_inf_fpu) {
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rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
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rtc_sleep_pu(pu_cfg);
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}
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return reject;
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}
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