menu "Hardware Settings" orsource "./port/$IDF_TARGET/Kconfig.spiram" menu "MAC Config" config ESP_MAC_ADDR_UNIVERSE_WIFI_STA bool config ESP_MAC_ADDR_UNIVERSE_WIFI_AP bool config ESP_MAC_ADDR_UNIVERSE_BT bool config ESP_MAC_ADDR_UNIVERSE_ETH bool # Insert chip-specific MAC config rsource "./port/$IDF_TARGET/Kconfig.mac" endmenu menu "Sleep Config" # This is here since this option affect behavior of esp_light_sleep_start # regardless of power management configuration. config ESP_SLEEP_POWER_DOWN_FLASH bool "Power down flash in light sleep when there is no SPIRAM" depends on !SPIRAM default y help If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs more time when chip wakes up. Can only be enabled if there is no SPIRAM configured. This option will in fact consider VDD_SDIO auto power value (ESP_PD_OPTION_AUTO) as OFF. Also, it is possible to force a power domain to stay ON during light sleep by using esp_sleep_pd_config() function. config ESP_SLEEP_RTC_BUS_ISO_WORKAROUND bool default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 config ESP_SLEEP_GPIO_RESET_WORKAROUND bool "light sleep GPIO reset workaround" default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE help esp32c2, esp32c3 and esp32s3 will reset at wake-up if GPIO is received a small electrostatic pulse during light sleep, with specific condition - GPIO needs to be configured as input-mode only - The pin receives a small electrostatic pulse, and reset occurs when the pulse voltage is higher than 6 V For GPIO set to input mode only, it is not a good practice to leave it open/floating, The hardware design needs to controlled it with determined supply or ground voltage is necessary. This option provides a software workaround for this issue. Configure to isolate all GPIO pins in sleep state. config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND bool "PSRAM leakage current workaround in light sleep" depends on SPIRAM help When the CS pin of SPIRAM is not pulled up, the sleep current will increase during light sleep. If the CS pin of SPIRAM has an external pull-up, you do not need to select this option, otherwise, you should enable this option. config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND bool "Flash leakage current workaround in light sleep" help When the CS pin of Flash is not pulled up, the sleep current will increase during light sleep. If the CS pin of Flash has an external pull-up, you do not need to select this option, otherwise, you should enable this option. config ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY int "Extra delay in deep sleep wake stub (in us)" depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 default 2000 range 0 5000 help When the chip exits deep sleep, the CPU and the flash chip are powered on at the same time. CPU will run deep sleep stub first, and then proceed to load code from flash. Some flash chips need sufficient time to pass between power on and first read operation. By default, without any extra delay, this time is approximately 900us, although some flash chip types need more than that. By default extra delay is set to 2000us. When optimizing startup time for applications which require it, this value may be reduced. If you are seeing "flash read err, 1000" message printed to the console after deep sleep reset, try increasing this value. endmenu menu "RTC Clock Config" orsource "./port/$IDF_TARGET/Kconfig.rtc" config RTC_CLOCK_BBPLL_POWER_ON_WITH_USB # This is used for configure the RTC clock. bool "Keep BBPLL clock always work" depends on ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG default y help When the chip goes sleep or software reset, the clock source would change to XTAL and switch off the BBPLL clock for saving power. However, this might make the USB_SERIAL_JTAG down which depends on BBPLL as its unique clock source. Therefore, this is used for keeping bbpll clock always on when USB_SERIAL_JTAG PORT is using. If you want to use USB_SERIAL_JTAG under sw_reset case or sleep-wakeup case, you shoule select this option. But be aware that this might increase the power consumption. endmenu menu "Peripheral Control" config PERIPH_CTRL_FUNC_IN_IRAM bool "Place peripheral control functions into IRAM" default n help Place peripheral control functions (e.g. periph_module_reset) into IRAM, so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. endmenu menu "MMU Config" # This Config is used for configure the MMU. # Be configured based on flash size selection. # Invisible to users. config MMU_PAGE_SIZE_16KB bool default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_1MB default n config MMU_PAGE_SIZE_32KB bool default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_2MB default n config MMU_PAGE_SIZE_64KB bool default y if !MMU_PAGE_SIZE_32KB && !MMU_PAGE_SIZE_16KB default n config MMU_PAGE_MODE string default "16KB" if MMU_PAGE_SIZE_16KB default "32KB" if MMU_PAGE_SIZE_32KB default "64KB" if MMU_PAGE_SIZE_64KB config MMU_PAGE_SIZE # Some chips support different flash MMU page sizes: 64k, 32k, 16k. # Since the number of MMU pages is limited, the maximum flash size supported # for each page size is reduced proportionally: 4 MB, 2MB, 1MB. To make best # use of small flash sizes (reducing the wasted space due to alignment), we # need to use the smallest possible MMU page size for the given flash size. hex default 0x4000 if MMU_PAGE_SIZE_16KB default 0x8000 if MMU_PAGE_SIZE_32KB default 0x10000 if MMU_PAGE_SIZE_64KB endmenu # Insert chip-specific HW config orsource "./port/$IDF_TARGET/Kconfig.hw_support" menu "GDMA Configuration" depends on SOC_GDMA_SUPPORTED config GDMA_CTRL_FUNC_IN_IRAM bool "Place GDMA control functions into IRAM" default n help Place GDMA control functions (like start/stop/append/reset) into IRAM, so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. Enabling this option can improve driver performance as well. config GDMA_ISR_IRAM_SAFE bool "GDMA ISR IRAM-Safe" default n help This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash cache misses, and also be able to run whilst the cache is disabled. (e.g. SPI Flash write). endmenu # GDMA Configuration endmenu