eeb5e2f080
Merge branch 'refactor/cpu_interrupt_table' into 'master'
...
refactor(Core System/Interrupts): changed reserved interrupt functions to be now defined per SoC
Closes IDF-5728
See merge request espressif/esp-idf!29020
2024-03-06 11:26:17 +08:00
ee02b71f1c
feat(esp32c61): introduce target esp32c61
2024-03-01 21:12:25 +08:00
7b414002f6
Merge branch 'change/psram_200m_update' into 'master'
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change(psram): update voltage configurations
See merge request espressif/esp-idf!28933
2024-03-01 15:17:24 +08:00
e18fd01d0d
Merge branch 'fix/pmp_idcache_reg_prot' into 'master'
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fix(esp_hw_support): Fix the I/DCACHE region PMP protection
See merge request espressif/esp-idf!28525
2024-02-29 21:39:11 +08:00
7adbc9cf4b
Merge branch 'fix/fix_key_manager_clock_changes' into 'master'
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fix(hal): Fix Key Manager clock changes
See merge request espressif/esp-idf!28890
2024-02-29 21:38:18 +08:00
f9109beda2
feat(uart): add HP/LP uart support on ESP32C5
2024-02-29 14:12:51 +08:00
4636ef946b
fix(esp_hw_support): Update key manager locking mechanism
2024-02-29 12:00:30 +08:00
62440e5b12
change(psram): update voltage configurations
2024-02-29 10:42:37 +08:00
c1849df791
refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC
2024-02-28 15:21:10 +08:00
366e4ee944
refactor(esp_hw_support): Remove redundant PMP entry for ROM region
...
- The ROM text and data sections share the address range
(see SOC_I/DROM_MASK_LOW - SOC_I/DROM_MASK_HIGH).
- Initially, we had two PMP entries for this address range - one marking the
region as RX and the other as R.
- However, the latter entry is redundant as the former locks the PMP settings.
- We can divide the ROM region into text and data sections later when we
define boundaries marking these regions from the ROM.
2024-02-28 10:54:38 +05:30
ff839be31d
fix(esp_hw_support): Fix the I/DCACHE region PMP protection
2024-02-28 10:54:37 +05:30
c7a02cbe55
Merge branch 'c6_auto_dbias_master_hsq' into 'master'
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ESP32C6: Active & sleep dbg and dbias get from efuse to fix the voltage
See merge request espressif/esp-idf!27696
2024-02-22 19:12:28 +08:00
90d1dcfd76
feat(freertos): Introduced new Kconfig option CONFIG_FREERTOS_NUMBER_OF_CORES
...
This commit replaces the use of portNUM_PROCESSORS and configNUM_CORES
macros in all of ESP-IDF. These macros are needed to realize an SMP
scenario by fetching the number of active cores FreeRTOS is running on.
Instead, a new Kconfig option, CONFIG_FREERTOS_NUMBER_OF_CORES, has been
added as a proxy for the FreeRTOS config option, configNUMBER_OF_CORES.
This new commit is now used to realize an SMP scenario in various places
in ESP-IDF.
[Sudeep Mohanty: Added new Kconfig option CONFIG_FREERTOS_NUMBER_OF_CORES]
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2024-02-09 09:11:28 +01:00
d556fee5c4
Merge branch 'feature/esp32c5_clock_preliminary_support' into 'master'
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Feature/esp32c5 clock preliminary support
See merge request espressif/esp-idf!28808
2024-02-08 11:54:35 +08:00
95133c179f
feat(clk): preliminary clock tree support for ESP32C5
2024-02-07 14:38:15 +08:00
dce27c3b09
change(clk_tree): add LP_DYN_FAST_CLK to soc_module_clk_t
2024-02-07 14:37:48 +08:00
ea14b24048
ci(esp32c5): fix the build of the template app
2024-02-05 12:39:35 +08:00
c0c6af99e9
fix(esp32c5): fixed the lack of crosscore ll on c5
2024-02-05 12:39:35 +08:00
35918b89a9
feat(pmu): set fix voltage to different mode for esp32c6 & c6 modify brownout rst2
2024-02-04 14:13:23 +08:00
0c2f811ca8
feat(esp_hw_support): support gdma register context sleep retention
2024-02-02 11:21:40 +08:00
6dbb3059f9
Merge branch 'h2_auto_dbias_master_hsq' into 'master'
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ESP32H2: Active & sleep dbias get from efuse to fix the voltage
See merge request espressif/esp-idf!27483
2024-01-29 10:16:15 +08:00
cf93777077
refactor(rtc): move soc/rtc.h from soc to esp_hw_support component
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Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
2024-01-25 19:15:33 +08:00
0b79d9bf4c
feat(pmu): set fix voltage to different mode for esp32h2
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h2 remove include
2024-01-24 13:11:41 +08:00
09c9001895
Merge branch 'feature/add_key_manager_hw_support' into 'master'
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Feature/add key manager hw support
Closes IDF-7925 and IDF-8041
See merge request espressif/esp-idf!26328
2024-01-23 17:11:05 +08:00
e3d4b901f9
Merge branch 'bugfix/compilation_failed_in_bootloader_with_sb_fe_verbose' into 'master'
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fix(bootloader): Fix compilation issue in bootloader build during verbose+sb+fe
Closes IDF-6373
See merge request espressif/esp-idf!26339
2024-01-23 13:29:02 +08:00
4dc2ace0b7
fix(esp_hw_support): Update key manager support
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1) Added new Key Manager APIs
2) Added crypto locking layer for Key Manager
3) Remove support for deploying known key
4) Format key manager support
5) Fix build header error
6) Updated the key_mgr_types.h file
7) Added key manager tests
2024-01-23 10:24:39 +05:30
9ecd2fd7e3
fix(soc): change debug addr range to CPU subsystem range
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For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).
For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.
For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-22 13:34:32 +08:00
102d5bbf72
refactor(riscv): added a new API for the interrupts
2024-01-18 16:36:53 +08:00
59c5b5fe6b
fix(bootloader): Fix compilation issue in bootloader build during verbose+sb+fe
2024-01-18 12:15:15 +05:30
6768805d20
fix(uart,usj...): Fix wrong serial number that has been parsed to rom functions,
...
Closes https://github.com/espressif/esp-idf/issues/12958
2024-01-18 10:51:51 +08:00
ce388a4111
feat(esp_eth): Added support of internal EMAC for ESP32P4
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Refactored internal EMAC DMA access.
Added MPLL acquire to manage access to the MPLL by multiple periphs.
2024-01-16 14:29:25 +01:00
80e18811db
feat(psram): support 200mhz psram, experimental feature for now
2024-01-10 11:52:28 +08:00
d0a8f3e5c4
feat(esp32c5): support esptool on esp32c5 beta3
2024-01-09 13:11:11 +08:00
3d459e423a
feat(esp32c5): support esp32c5 beta3 48M xtal
2024-01-09 13:11:11 +08:00
11e19f40b9
feat(esp32c5): support to build hello world on esp32c5 beta3
2024-01-09 13:11:11 +08:00
b74cc4637b
Merge branch 'feature/support_hw_trigger_regdma_when_pu_top' into 'master'
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fix(pm): trigger regdma retention by PMU when TOP is not power down on esp32H2
Closes PM-47 and PM-65
See merge request espressif/esp-idf!28046
2024-01-08 10:44:06 +08:00
aed3127d19
feat(pm): support PMU trigger regdma when PU TOP
2024-01-05 16:17:32 +08:00
c204f418ef
fix(rtc): fixed bbpll not calibrated from bootloader issue
2024-01-04 03:23:20 +08:00
8775b99d93
fix(bbpll): fix bbpll calibration may stop early bug(ESP32C2/S3/C6/H2)
2024-01-04 03:23:20 +08:00
a48f4760d2
feat(esp32c5): add system related supports
2024-01-02 11:17:11 +08:00
7f2b85b82b
feat(clk): add basic clock support for esp32p4
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- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
2023-12-29 00:37:26 +08:00
71202c701f
change(ldo): do vddpst ldo init in early stage
2023-12-26 11:43:33 +08:00
27b1e4dc87
feat(mpll): supported mpll configure ll api
2023-12-21 16:26:03 +08:00
73de93d55e
Merge branch 'bugfix/wait_tvsl_after_non_pd_top_lightsleep_for_esp32c6' into 'master'
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fix(esp_hw_support/sleep): wait flash ready after non-pd_top lightsleep for esp32c6
Closes IDF-6930
See merge request espressif/esp-idf!27726
2023-12-19 14:01:45 +08:00
d8b1f7207a
change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG
2023-12-15 15:04:06 +08:00
7de2728733
fix(esp_hw_support/sleep): wait flash ready after non-pd_top lightsleep for esp32c6
2023-12-14 08:57:06 +00:00
80c2bd3d7c
Merge branch 'bugfix/put_extra_link_retention_in_iram' into 'master'
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fix(pm): place extra link opt in iram
Closes PM-30
See merge request espressif/esp-idf!27625
2023-12-14 10:28:34 +08:00
ac3915f092
docs(esp32p4): update misc docs for esp32p4
2023-12-09 09:09:55 +08:00
e1d24ebd7f
fix(esp_hw_support/sleep): fix rtc_time_us_to_slowclk div zero in deepsleep process
...
Closes https://github.com/espressif/esp-idf/issues/12695
2023-12-07 07:50:32 +00:00
797edb54fa
fix(pm): place extra link opt in iram
2023-12-04 14:46:42 +08:00
Omar Chebib