In some cases, when data was just written into UART FIFO, transmitter
state could be still zero while the FIFO did contain some data.
This resulted in uart_tx_wait_idle occasionally returning before all
the data was sent out.
Fix by checking both UART transmitter state and TX FIFO count.
- ROM function uart_tx_wait_idle may have a bug which causes the function to return before the final character is fully transmitted.
This replaces uart_tx_wait_idle declaration with a static inline definition which fixes the issue.
- Also replaces the use of uart_tx_flush with uart_tx_wait_idle in esp_restart, to remove garbage in console output on restart.
- rtc_printf is temporary replaced with a no-op, pending a new release of librtc.a. Current release assumes that UART0 is used for output,
and switches UART0 baud rate while doing frequency changes and printing some log output. This doesn’t work if a different UART is used for output.
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
Ivan Grokhotkov