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28 518 Commity
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69 Commity (b7382c60f982ba43379d4f467068e7bbec18af94)

Autor SHA1 Wiadomość Data
hongshuqing 44815d75eb fix: fix_maximum_value_of_config_rtc_clk_cal_cycle_bug 2024-03-14 16:22:39 +08:00
Xiao Xufeng 376be14e1c fix(rtc): fixed bbpll not calibrated from bootloader issue 2024-01-14 02:38:49 +08:00
chaijie@espressif.com d91c6d0da8 fix(bbpll): fix bbpll calibration may stop early bug(ESP32C2/S3) 2024-01-05 03:36:48 +08:00
Jakob Hasse 900ee4e7a6 fix(esp_hw_support): Removed unused include directories from cmake 
* Closes https://github.com/espressif/esp-idf/issues/12700
 2023-12-04 14:12:18 +08:00
harshal.patil 6fdbd027c5
feat(esp_hw_support): Add locking layer for the ECC peripheral 2023-09-29 11:24:34 +05:30
wuzhenghui 652bc76354 fix(lightsleep): fix access pu_cfg after sleep wakeup which is linked to flash 2023-07-31 21:36:27 +08:00
Michael (XIAO Xufeng) 1b04acf68f Merge branch 'bugfix/fix_chip_broken_bug_in_monitor_mode_c2c3s2s3_to_v5.0' into 'release/v5.0' 
ESP32S2/C3/C2: fixed S2 dangerous power parameters in sleep modes and support S2/C3/C2 different sleep mode(v5.0)

See merge request espressif/esp-idf!23754
 2023-06-13 17:50:21 +08:00
hongshuqing d82af7f54a fix chip broken bug in monitor mode for c2 c3 s2 s3 to v5.0 2023-06-13 10:22:40 +08:00
Jiang Jiang Jian 838850abab Merge branch 'feature/example_deep_sleep_wake_stub_backport_v5.0' into 'release/v5.0' 
example: add deepsleep_wake stub example (backport v5.0)

See merge request espressif/esp-idf!23414
 2023-06-12 11:07:59 +08:00
jiangguangming 4261fd0940 rtc_time.c: simplify the rtc_time_get with LL function 2023-05-04 16:46:15 +08:00
Armando 08c77a7eaf sar: init sar periph power state 2023-04-27 10:52:38 +08:00
Li Shuai d84cdace52 sleep: fix sleep current issue caused by sar adc 2023-04-20 11:45:58 +08:00
Armando 85980884d7 adc: improve adc power logic 2023-04-20 10:34:37 +08:00
Jiang Jiang Jian 335ad04cba Merge branch 'feature/support_feature_depend_on_rtc_fast_mem_for_esp32c2_backport_v5.0' into 'release/v5.0' 
esp32c2: support feature(rtc time) depend on rtc fast mem(backport v5.0)

See merge request espressif/esp-idf!22224
 2023-02-27 15:06:31 +08:00
zlq bd7bcbb03b 1.add ldo parameters in efuse table; 2.set ldo dbias based on pvt-efuse; 3.add pll cali stop function; 4. add efuse_ocode 2023-02-20 10:33:25 +08:00
jingli ac47b093f6 esp32c2/rtc: fix 8md256 as rtc slow clk not work properly during deep sleep 2023-02-16 10:55:50 +08:00
jingli e109c5f998 esp32c2: support rtc time feature depend on rtc memory, since c2 does not have rtc memory 2023-02-16 10:52:59 +08:00
Michael (XIAO Xufeng) ac068eed34 esp32c2: fixed chip revision of ECO2 2023-01-06 02:00:52 +08:00
KonstantinKondrashov d130b5b6ba esp_hw_support: Removes esp32c2 eco2 support 2023-01-06 02:00:52 +08:00
Michael (XIAO Xufeng) bb0c26c233 esp32c2: put v2.0 back to development stage 2023-01-06 02:00:52 +08:00
KonstantinKondrashov 823024c10c all: Apply new version logic (major * 100 + minor) 2023-01-06 02:00:52 +08:00
Marius Vikhammer 7cd7056341 hw-support: update C2 chip info to reflect that esp8684 has embedded flash 
Closes https://github.com/espressif/esp-idf/issues/10175
 2022-12-05 02:29:46 +00:00
jingli 9fa4bb272e esp_hw_support/clk_cali: fix xtal32k error detect 2022-09-21 16:21:11 +08:00
zlq 3dc89437cc support auto adjust LDO voltage based on pvt-dig 2022-08-17 17:25:59 +08:00
jingli d3d1d4e1df esp32c2/clk_cali: fix rtc slow clk cali logic 2022-08-17 11:17:36 +08:00
jingli 8cd7c30bc7 kconfig: refactor xtal freq kconfig to common configuration item 2022-08-08 13:53:02 +08:00
morris 031adc01c4 gpio: add test with -O0 2022-08-02 23:07:06 +08:00
morris 5e50ec1d66 systimer: add helper functions to convert between tick and us 2022-07-25 16:08:52 +08:00
Guillaume Souchere 6005cc9163 hal: Deprecate interrupt_controller_hal.h, cpu_hal.h and cpu_ll.h interfaces 
This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
 2022-07-22 00:06:06 +08:00
songruojing ef813b23fa rtc: esp32c2 support 26MHz xtal in startup code and rtc_clk.c 2022-07-11 12:24:58 +08:00
Ivan Grokhotkov 672e70a023 esp_hw_support: add 26 MHz XTAL option for esp32c2 
Some esp32c2 boards will be produced with a 26 MHz XTAL. This commit
adds the basic Kconfig option for this type of hardware.
Support for CONFIG_ESP32C2_XTAL_FREQ_26 in other areas of IDF will be
implemented in subsequent commits.
 2022-07-08 15:04:17 +08:00
Michael (XIAO Xufeng) a58362a429 Merge branch 'feature/efuse_rev_major_minor' into 'master' 
efuse: Adds major and minor versions

See merge request espressif/esp-idf!18255
 2022-07-07 11:48:54 +08:00
Song Ruo Jing b662f4b74f Merge branch 'feature/support_26M_32M_xtal_bbpll_c2' into 'master' 
support c2 26M/32M xtal for bbpll

Closes IDF-5485

See merge request espressif/esp-idf!18769
 2022-07-06 21:17:52 +08:00
cje e16165f263 support c2 26M/32M xtal for bbpll 2022-07-05 17:45:03 +08:00
KonstantinKondrashov 0f8ff5aa15 efuse: Adds major and minor versions and others 2022-07-05 14:38:27 +08:00
Omar Chebib cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component 
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
 2022-06-30 09:40:44 +00:00
morris 7fd9a91034 dma: move from driver to hw_support 2022-06-28 14:17:12 +08:00
Omar Chebib 8fae0f0753 G0: Support Xtensa targets for G0-only compilation 
G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
 2022-06-20 11:34:20 +00:00
Omar Chebib 752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' 
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
 2022-06-16 11:53:39 +08:00
Darian e213e66ba3 Merge branch 'refactor/esp_hw_support_cpu' into 'master' 
esp_hw_support: Add new esp_cpu.h abstraction

Closes IDF-4769

See merge request espressif/esp-idf!17091
 2022-06-14 21:11:30 +08:00
Omar Chebib 2fd784c97a G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h" 2022-06-14 15:00:53 +08:00
Omar Chebib 5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer 
G0 doesn't depend on any G1+ layer for RISC-V based targets
 2022-06-14 15:00:53 +08:00
Darian Leung 61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API 
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
 2022-06-14 14:30:58 +08:00
Darian Leung 556ec30457 esp_hw_support: Rename cpu_util.c to cpu.c 2022-06-14 14:30:57 +08:00
songruojing 03477a59db rtc_clk: Fix rtc8m calibration failure after cpu/core reset 
1. make sure 8md256 clk is enabled before calibration
2. improve bootloader and application startup 8m, 8md256 enable logic
 2022-06-13 17:47:51 +08:00
songruojing c8752cee6a clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem 2022-06-13 17:47:50 +08:00
KonstantinKondrashov ac4c7d99fe dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
jingli 9eec740a16 enable external 32k osc for esp32c2 2022-05-27 19:29:29 +08:00
Song Ruo Jing cf32e49aeb Merge branch 'refactor/cleanup_rtc_h' into 'master' 
clk_tree: Prework2 of introducing clock subsystem control

Closes IDF-4934

See merge request espressif/esp-idf!17861
 2022-05-26 09:16:47 +08:00
Sachin Parekh 9a763f4ff2 esp32c2: Enable IRAM/DRAM split using PMP 2022-05-24 21:36:06 +05:30