9d7bd6a8dd
change(esp_phy): Add SOC_PHY_SUPPORTED to control phy mode
2024-04-01 11:36:55 +08:00
c07be48edb
change(esp_hw_support): add adc retention module and it is dependencies on the clock modem
2024-03-30 11:51:52 +08:00
59115cd2d1
change(esp_hw_support): some system peripherals to use a retention module number
2024-03-29 15:27:08 +08:00
080d09387c
change(esp_hw_support): modify the style of module argument from bitmap to number
2024-03-29 15:22:52 +08:00
4a64d2fe2c
change(hal): control PAU bus clock by hal layer
2024-03-29 00:36:46 +08:00
a307096ec0
spi_master: sct mode supported on c6
2024-03-20 15:42:03 +08:00
4971764917
feat(esp_wifi): Refactor and improve FTM code
...
Enable FTM Responder mode for ESP32C6. Update wifi libs with below -
1. Break FTM State Machine code into separate functions
2. Use dynamic allocation for FTM session to save memory
3. Add API to get FTM report instead of event based mechanism
4. Add FTM Request retry and comeback support
Closes https://github.com/espressif/esp-idf/issues/6810
2024-03-18 22:01:36 +08:00
8de41350eb
feat(esp32c5mp): support to build g0 components
2024-03-14 15:09:22 +08:00
5a682c3bbb
Merge branch 'feature/optimize_chips_active_power' into 'master'
...
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state
Closes IDF-5658
See merge request espressif/esp-idf!27798
2024-03-14 12:08:33 +08:00
0fc97f0e84
feat(gpio): support LP_IO clock gating management
2024-03-13 11:56:14 +08:00
9e8e20227f
feat(system): disable RNG module clock by default for save power
2024-03-12 10:10:41 +08:00
fd6c710b27
fix: cleanup memprot files for C6/H2/P4
...
There is no separate permission control peripheral in C6/H2/P4.
Memory protection is achieved using built-in PMA/PMP and hence
removing permission control specific files.
2024-03-11 17:10:40 +05:30
85b246ac88
feat(system): gate the debug clock source by default for esp32c6 and esp32h2
2024-03-07 19:26:39 +08:00
0b9f01ac20
feat(soc): Add soc_caps macros for sleep support
...
- modify console example to use the new SOC_LIGHT_SLEEP_SUPPORTED
and SOC_DEEP_SLEEP_SUPPORTED macros when registering sleep commands
- remove exclusion of esp32p4 in basic and advanced example in
.build-test-rules.yml
- replace exclusion of esp32p4 for deep and light sleep tests with newly introduced macro
- remove the temporary disable check for esp32p4 and uses the
SOC_LIGHT_SLEEP_SUPPORTED maccro instead.
2024-03-05 07:05:40 +01:00
0f03434119
Merge branch 'feature/tsens_etm' into 'master'
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feature(temperature sensor): Temperature sensor ETM support.
Closes IDF-6357
See merge request espressif/esp-idf!28880
2024-03-05 10:09:25 +08:00
2b2b3be98f
feat(temperature_sensor): Add new support for temperature sensor ETM on ESP32C6/H2
2024-03-01 18:52:39 +08:00
7075b61a6a
docs(uart): update lp uart and p4/c5 uart programming guide
2024-03-01 16:21:22 +08:00
98d9f04b00
feat(gdma): add GDMA support for ESP32C5
2024-02-28 12:38:02 +08:00
cf521b60ea
feat(i2c): Support i2c sleep retention on esp32c6/h2
2024-02-23 11:28:14 +08:00
c7a02cbe55
Merge branch 'c6_auto_dbias_master_hsq' into 'master'
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ESP32C6: Active & sleep dbg and dbias get from efuse to fix the voltage
See merge request espressif/esp-idf!27696
2024-02-22 19:12:28 +08:00
c0a2043562
fix(system): update reset reasons for C6 and H2
2024-02-20 12:27:09 +08:00
5276cd4f1d
refactor(uart): add support to be able to test LP_UART port
...
Increase LP_UART_EMPTY_THRESH_DEFAULT value to 4. The original value
could cause the FIFO become empty before filling next data into the FIFO
when the buadrate is high. TX_DONE interrupt would raise before actual
transmission complete in such case.
2024-02-07 14:37:48 +08:00
35918b89a9
feat(pmu): set fix voltage to different mode for esp32c6 & c6 modify brownout rst2
2024-02-04 14:13:23 +08:00
0c2f811ca8
feat(esp_hw_support): support gdma register context sleep retention
2024-02-02 11:21:40 +08:00
cf93777077
refactor(rtc): move soc/rtc.h from soc to esp_hw_support component
...
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
2024-01-25 19:15:33 +08:00
55f04b3326
Merge branch 'feature/clean_up_retention_context_definitions' into 'master'
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refactor(esp_hw_support): move sleep retention context definition to soc target folder
Closes PM-10
See merge request espressif/esp-idf!26753
2024-01-24 20:24:02 +08:00
f3f12e973c
refactor(esp_hw_support): separate different chip system peripheral regs context defs to target folder
2024-01-23 13:30:01 +08:00
9b3dc69908
refactor(esp_hw_support): move regdma structure defination to soc components
2024-01-23 11:51:44 +08:00
9ecd2fd7e3
fix(soc): change debug addr range to CPU subsystem range
...
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).
For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.
For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-22 13:34:32 +08:00
261651fc19
Merge branch 'feature/efuse_update' into 'master'
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feat(efuse): Adds new efuses for H2 and C6 chips
See merge request espressif/esp-idf!27672
2024-01-20 03:10:44 +08:00
102d5bbf72
refactor(riscv): added a new API for the interrupts
2024-01-18 16:36:53 +08:00
ba0842a552
feat(efuse): Adds new efuses for esp32c6
2024-01-16 17:46:50 +08:00
0bf2b35b33
fix(i2c): Use hardware fsm reset on esp32c6/h2/p4
2024-01-16 10:05:05 +08:00
83d5797967
Merge branch 'feature/parlio_rx_driver' into 'master'
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driver: add parallel IO RX driver
Closes IDF-7002 and IDF-6984
See merge request espressif/esp-idf!23488
2023-12-29 16:36:24 +08:00
7f2b85b82b
feat(clk): add basic clock support for esp32p4
...
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
2023-12-29 00:37:26 +08:00
04d267b023
feat(parlio_rx): implement parallel io rx driver
2023-12-27 19:32:12 +08:00
439bc719fe
feat(temperature_sensor): Add temperature sensor support on esp32p4
2023-12-26 16:45:20 +08:00
6cef08c03d
feat(ieee802154): add tx/rx report for IEEE802.15.4 debug
2023-12-14 12:29:57 +08:00
2b44d62e43
feat(esp32c5): support esp32c5 g0 components
2023-12-08 15:12:24 +08:00
2c32bd209a
change(fpga): added bypass rng configuration
2023-12-05 11:38:35 +08:00
5f4865e838
Merge branch 'doc/soc_cap_tool' into 'master'
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Doc/soc cap tool
See merge request espressif/esp-idf!27154
2023-11-23 10:47:01 +08:00
72e414105d
Merge branch 'contrib/github_pr_12559' into 'master'
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fix(spi): correct macro REG_SPI_BASE(i) for all targets (GitHub PR)
Closes IDFGH-11421 and IDFGH-11424
See merge request espressif/esp-idf!27085
2023-11-20 15:55:41 +08:00
9fb38d82a3
Merge branch 'fix/rng_register_prefix_discrepency_newer_targets' into 'master'
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Fix: RNG register prefix discrepancy for ESP32C6 and ESP32H2
Closes DOC-5161 and DOC-5175
See merge request espressif/esp-idf!27212
2023-11-20 10:53:09 +08:00
46e44ee154
docs(soc): improved soc caps generation documentation
2023-11-17 10:43:59 +08:00
4dcd6d7913
fix(spi): correct some signals and dummy bits docs
2023-11-17 02:39:28 +00:00
90eada6993
fix(spi): Correct REG_SPI_BASE(i) macro for all targets
...
The existing formula can never match these registers.
Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
2023-11-17 02:39:28 +00:00
798059ace1
fix(soc/esp32c6): Fix llperi_rng_data field discrepancy
2023-11-16 17:49:26 +05:30
161bd8bfed
change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
2023-11-16 18:11:57 +08:00
46d33e46ef
fix(console): enable to select UART1 port for console output
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This feature was only enabled for esp32, esp32s2, esp32s3 previously.
Now, enabling this feature for all targets.
2023-11-09 22:32:49 +08:00
4111b07076
Merge branch 'bugfix/flash_enc_plaintext' into 'master'
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fix(flash_encryption): Fix the issue that XTS_AES Plain text memory size wrong
See merge request espressif/esp-idf!26640
2023-10-27 18:23:00 +08:00
xiehang