9 Commity (8fbece32a989bb578cdce4983d80736bccd7b94f)

Autor	SHA1	Wiadomość	Data
David Cermak	8f91d730da	make: fix build failure on macos with GNU make <= 3.81 ... Closes https://github.com/espressif/esp-idf/issues/3459	2019-05-16 14:09:43 +02:00
Michael (XIAO Xufeng)	af2fc96ee1	spi_master: refactor and add HAL support	2019-03-28 17:14:50 +08:00
Renz Bagaporo	63411fc556	tools: implement linker script generation	2018-11-16 12:42:02 +08:00
Ivan Grokhotkov	ccfa134533	build system: support for multiple targets	2018-11-11 21:46:02 +08:00
Ivan Grokhotkov	e59571eece	soc/rtc_clk: reduce data size by disabling CSWTCH generation ... Saves about 200 bytes of DRAM at the expense of 4 bytes in IRAM.	2018-08-21 13:02:46 +08:00
Angus Gratton	a5ae5ac4b3	soc: Allow components to reserve fixed memory ranges that they need ... No longer necessary to keep all reserved addresses in 'soc'. Means 'soc' does not need to know about 'bt', for example. Also means that Bluetooth can be enabled in config without any memory being reserved for BT controller. Only if code calling the BT controller is linked in, will this memory be reserved...	2018-08-06 01:37:55 +00:00
Jeroen Domburg	34372a091c	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00
Angus Gratton	71c70cb15c	heap: Refactor heap regions/capabilities out of FreeRTOS ... Remove tagged heap API, rename caps_xxx to heap_caps_xxx Also includes additional heap_caps_xxx inspection functions.	2017-07-10 17:46:03 +08:00
Ivan Grokhotkov	7ee8ee8b7e	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00