Wykres commitów

30 Commity (8efc66495bb9a27c8326de42d857c34c2721d57a)

Autor SHA1 Wiadomość Data
Darian Leung d33e551f47 freertos: Remove GPL license text from port files
This commit removes the GPL license text from various FreeRTOS port files as it
no longer matches the licensing of FreeRTOS v10.4.3 which is distributed under
the MIT license.
2022-12-13 19:29:24 +08:00
Omar Chebib b2ddedb941 FreeRTOS: Make the default stack alignment 16 for Xtensa 2022-12-02 15:20:09 +08:00
Alexey Gerenkov 9017ff235b riscv: Use semihosting to set breakpoint and watchpoint when running under debugger 2022-05-13 12:54:21 +03:00
Alexey Gerenkov 300d67411a riscv: Fixes GDB backtrace end function to point to prvTaskExitError 2022-05-13 12:52:06 +03:00
Marius Vikhammer f3639dafc8 freertos: add pm_trace header include 2022-02-17 22:22:26 +08:00
Darian Leung c5efb55d43 freertos: Add portTRY_ENTRY_CRITICAL() and deprecate legacy spinlock fucntions
Add TRY_ENTRY_CRITICAL() API to all for timeouts when entering critical sections.
The following port API were added:
- portTRY_ENTER_CRITICAL()
- portTRY_ENTER_CRITICAL_ISR()
- portTRY_ENTER_CRITICAL_SAFE()

Deprecated legacy spinlock API in favor of spinlock.h. The following API were deprecated:
- vPortCPUInitializeMutex()
- vPortCPUAcquireMutex()
- vPortCPUAcquireMutexTimeout()
- vPortCPUReleaseMutex()

Other Changes:
- Added portMUX_INITIALIZE() to replace vPortCPUInitializeMutex()
- The assembly of the critical section functions ends up being about 50 instructions longer,
  thus the spinlock test pass threshold had to be increased to account for the extra runtime.

Closes https://github.com/espressif/esp-idf/issues/5301
2021-11-22 18:42:10 +08:00
Darian Leung 7e725751e4 freertos: Remove critical nested macros
This commit removes the following critical nested macros as follows:

- portENTER_CRITICAL_NESTED()
- portEXIT_CRITICAL_NESTED()

They are replaced with portSET_INTERRUPT_MASK_FROM_ISR() and
portCLEAR_INTERRUPT_MASK_FROM_ISR() which are the proper FreeRTOS interfaces.

Created a portmacro_deprecated.h for each port to contain deprecated API
that were originally from portmacro.h
2021-11-10 18:34:32 +08:00
Darian Leung e194113964 freertos: Tidy up port files
- port.c and portmacro.h contents are now logically grouped
- Doxygen API descriptions added
- Added refactor todo markers
- Removed portmacro_priv.h. Contents now in portmacro.h
- Formatted files
2021-09-24 18:14:33 +08:00
Konstantin Kondrashov 29f581fc70 freertos(esp32s3): SysTick uses systimer 2021-08-04 20:33:44 +08:00
Alexey Gerenkov 20fd09728f apptrace: Adds ESP32-C3 support 2021-06-24 13:16:14 +03:00
morris ec898b771e systimer: strip hal driver 2021-04-22 21:08:39 +08:00
Ivan Grokhotkov 0535195983 freertos: fix TLS run-time address calculation
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.

Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.

Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
2021-04-21 13:45:21 +02:00
Angus Gratton fd164b82b6 Merge branch 'refactor/move_from_xtensa' into 'master'
Movements from xtensa

Closes IDF-2164

See merge request espressif/esp-idf!10556
2021-03-11 00:24:25 +00:00
Angus Gratton 3ddfe1e8ac Merge branch 'bugfix/asserts_disabled' into 'master'
core: Fix assert path embedding, warnings when asserts are disabled

Closes IDFGH-4477

See merge request espressif/esp-idf!12371
2021-03-03 08:20:54 +00:00
Angus Gratton d6f4d99d93 core system: Fix warnings in compilation when assertions are disabled
Adds a CI config for hello world that sets this, to catch future regressions
2021-03-03 10:26:57 +11:00
Renz Bagaporo 0f03f450ff esp_hw_support: create esp_cpu
Create a esp_cpu header that contains CPU-related functions and
utilities.
2021-02-26 13:34:29 +08:00
Omar Chebib 78a94dbb6c freertos: Fix delay between interrupt request and trigger on RISC-V
NOP instructions have been added in order to prevent the code
from executing code it shouldn't execute. This is due to a delay
between the moment an interrupt is requested and the moment it
is fired. It only happens on RISC-V SoC.
2021-02-25 06:57:59 +00:00
Marius Vikhammer 311a0fa5e8 freertos: add API for getting tick rate on C3 2021-02-23 12:05:52 +08:00
Marius Vikhammer eec2419390 system: enable shared stack watchpoint
Enable shared stack watchpoint for overflow detection

Enable unit tests:
 * "test printf using shared buffer stack" for C3
 * "Test vTaskDelayUntil" for S2
 * "UART can do poll()" for C3
2021-02-18 15:38:30 +08:00
Ivan Grokhotkov bb1f75179b Merge branch 'bugfix/freertos_systimer_stall_when_cpu_halted' into 'master'
freertos: stall systimer while CPU is in debug mode

See merge request espressif/esp-idf!12063
2021-01-29 07:02:30 +08:00
Ivan Grokhotkov b2aaebaf85 freertos: add thread local storage support in RISC-V port 2021-01-24 12:38:15 +00:00
Ivan Grokhotkov d7bac619ec freertos: stall systimer while CPU is in debug mode 2021-01-24 11:32:17 +00:00
Li Shuai 63c4e5481f fix no RTOS SysTick interrupt for a period of time after the OS Scheduler is started 2021-01-19 14:51:22 +08:00
Li Shuai 355dd10257 light sleep: dfs support for esp32c3 2021-01-19 14:50:58 +08:00
Jakob Hasse b51889dccb system: stack watchpoint support on C3
Closes IDF-2307
2021-01-14 17:46:44 +08:00
morris 9e7d2c0065 esp32c3: format and clean up interrupt and os port code 2021-01-05 15:39:46 +08:00
Felipe Neves f4781d3b1d freertos: riscv port now uses interrupt allocator and crosscore interrupt 2021-01-05 15:39:46 +08:00
Felipe Neves 810be86f21 freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port.
The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
2021-01-05 15:39:46 +08:00
Angus Gratton 5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Angus Gratton 87e13baaf1 freertos: Add RISC-V port
Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00