components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt
components/os: high level interrupt(5)
components/os: hli_api: meta queue: fix out of bounds access, check for overflow
components/os: hli: don't spill registers, instead save them to a separate region
Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).
Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.
components/bt: using high level interrupt in lc
components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`
components/bt: optimize code structure
components/os: Modify the BT assert process to adapt to coredump and HLI
components/os: Disable exception mode after saving special registers
To store some registers first, avoid stuck due to live lock after disabling exception mode
components/os: using dport instead of AHB in BT to fix live lock
components/bt: Fix hli queue send error
components/bt: Fix CI fail
# Conflicts:
# components/bt/CMakeLists.txt
# components/bt/component.mk
# components/bt/controller/bt.c
# components/bt/controller/lib
# components/esp_common/src/int_wdt.c
# components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
# components/soc/esp32/include/soc/soc.h
eh_frame_parser is architecture independent, thus the files have
been rearchitectured. Some bugs have been fixed in the test.
A README file has also been added to eh_frame_parser host test
directory.
eh_frame_parser is now able to detect empty gaps in .eh_frame_hdr
table (missing DWARF information).
Fix a bug occuring when parsing backtraces originated from abort().
Fix build missing dependencies issue.
Add .eh_frame and .eh_frame_hdr sections to the binary (can be
enabled/disabled within menuconfig). These sections are parsed
when a panic occurs. Their DWARF instructions are decoded and
executed at runtime, to retrieve the whole backtrace. This
parser has been tested on both RISC-V and x86 architectures.
This feature needs esptool's merge adjacent ELF sections feature.
Copy the esp32c3 code without any change:
* components/esp_hw_support/include/soc/esp32h2
* components/esp_hw_support/port/esp32h2
* components/esp_system/port/soc/esp32h2
This is mostly important on ESP32 ECO3 with the
ESP32_ECO3_CACHE_LOCK_FIX, because when we stall the other CPU core
before we disable the TG1 WDT then the first CPU can get stuck
in WDT ISR handle_livelock_int routine waiting for the other CPU.
Check Memprot lock bit(s) during the system startup, abort/reset on any Memprot parts found locked during this phase.
There is no legal reason to disallow the Memprot configuration by the system, so it's either a critical bug in the
application or an malicious attempt to bypass the system security.
Error message is printed before digital system reset.
Closes IDF-2700
By unchecking "Place panic handler code in IRAM" in the menuconfig,
the panic handlers will be placed in flash. Of course, flash cache must
be activated when entering panic handlers.
Armando