5 Commity (54b431f2a8b8d4e778ee94d2cfb10d55ccb72465)

Autor	SHA1	Wiadomość	Data
Wangjialin	6e9c59bfc3	feature(psram): add support for 64MBit psram of 1.8v and 3.3v. ... 1. Add reading psram EID. 2. Configure different clock mode for different EID. 3. add API to get psram size and voltage. 4. Remove unnecessary VSPI claim. For 32MBit@1.8V and 64MBit@3.3V psram, there should be 2 extra clock cycles after CS get high level. For 64MBit@1.8 psram, we can just use standard SPI protocol to drive the psram. We also need to increase the HOLD time for CS in this case. EID for psram: 32MBit 1.8v: 0x20 64MBit 1.8v: 0x26 64MBit 3.3v: 0x46	2018-07-10 14:24:59 +08:00
Ivan Grokhotkov	1da3204a7c	spiram: expose function to initialize SPI RAM cache ... Some frameworks based on ESP-IDF need to be able to decide whether to initialize SPI RAM after the application has started. This change splits out part of esp_spiram_init which manipulate cache MMU into a separate function. Applications can disable cache, call esp_spiram_init_cache, re-enable cache, and then call esp_spiram_init. Disabling and re-enabling the cache can be achieved using functions provided in esp_spi_flash.h.	2017-10-16 09:15:11 +08:00
Jeroen Domburg	740f8a79f0	Add logic to make external RAM usable with malloc()	2017-09-28 17:17:50 +08:00
Jeroen Domburg	875ae6a134	Add option to allocate external RAM using heap_alloc_caps	2017-09-14 10:47:44 +08:00
Jeroen Domburg	34372a091c	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00