- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
Probably GCC-13.x and on-wards uses "-fmerge-constants" to merge
the const section (string/floating-point) across compilation units.
This makes it difficult to properly analyze the size output of rodata
section across libraries, the merged section (big in size) is showed
across a single library.
The config option added here can help to disable this compiler behavior
and help to provide better size analysis. It can be used during
development phase only as it increases rodata section size.
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
The -Werror=all activates error for all warnings in -Wall, however, it
does not activate error for other default warnings, such as:
- int-conversion (pointer from integer w/o a cast)
- incompatible-pointer-types
- discarded-qualifiers
Which are IMO even more important that -Wall.
This commit fixes that by activating error for all warnings (i.e. from
-Wall and default ones) and removing those from -Wextra, as the culprit
commit seemed to address.
Fixes: 60f29236f6 "Build system: Raise warning level" (2016-11-16)
In order to avoid long analysis during esp-idf upgrade, provide a way to
restore the previous -Werror=all behavior that consider only warnings
from -Wall (and not default ones).
Also add a hint to use the Kconfig option on compilation error, but warn
that fixing the code is the preferred way.
Merges https://github.com/espressif/esp-idf/pull/11239
Suggested-By: Ivan Grokhotkov <ivan@espressif.com>
This commit makes v10.5.1 the default FreeRTOS kernel in ESP-IDF by removing
the CONFIG_FREERTOS_USE_KERNEL_10_5_1 option and v10.4.3 specific code
blocks.
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32h2
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
Song Ruo Jing