8 Commity (244cf14ea889e6a047a8337c693e52eb2cef5f86)

Autor	SHA1	Wiadomość	Data
Cao Sen Miao	2c9bb4eb7d	spi_flash: Support select flash mode automatically at run time(Quad flash or Octal flash)	2022-10-18 11:25:35 +08:00
wangyuanze	8781a50abe	spi_flash: fix hpm dummy error when using 80m flash and psram	2022-07-28 14:32:30 +08:00
Cao Sen Miao	ec6a56ed0c	spi_flash: re-enable the HPM mode on several XMC chips	2022-07-22 09:54:56 +08:00
Armando	c331c85318	mspi: make cpu clock source switch safe ... For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required. Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be cleared. When system clock switches up, the delays should be restored.	2021-10-19 21:47:27 +08:00
Cao Sen Miao	6c0aebe279	esp_flash: add opi flash support in esp_flash chip driver, for MXIC	2021-09-07 14:44:40 +08:00
Armando	a3dc625da6	mspi: support 120MHz Quad Flash and PSRAM on ESP32S3	2021-08-31 16:06:44 +08:00
Armando	2b52f7f696	mspi: fix no buffer reset before each psram read issue ... In psram timing tuning driver, we rely on psram read and write functions defined in `spi_timing_config.c`. If we don't do buffer reset (clear to 0), the function may untouch the buffer, which will keep last time value (since we reuse the buffer). Therefore, if the first read is expected, but next few reads didn't modify the buffer content, we will still see the expected data. These functions relies on `esp_rom_opiflash_exec_cmd`.	2021-08-03 16:54:01 +08:00
Renz Bagaporo	844af01eb4	esp32: move spiram, himem	2021-07-16 20:14:26 +08:00