esp-idf

Wykres commitów

Autor	SHA1	Wiadomość	Data
Angus Gratton	87e13baaf1	freertos: Add RISC-V port Changes come from internal branch commit a6723fc	2020-11-13 07:49:11 +11:00
Sachin Parekh	301dacfb33	Exception handlers for LoadStoreError and LoadStoreAlignmentError Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection.	2020-02-26 20:21:59 +08:00

Autor

SHA1

Wiadomość

Data

Angus Gratton

87e13baaf1

freertos: Add RISC-V port

Changes come from internal branch commit a6723fc

2020-11-13 07:49:11 +11:00

Sachin Parekh

301dacfb33

Exception handlers for LoadStoreError and LoadStoreAlignmentError

Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.

2020-02-26 20:21:59 +08:00

2 Commity (0159c37cf27b3c2ec137760ecfda8ffe621388ef)