diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 27d6bbbe26..2319e391ee 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -30,10 +30,9 @@ #include "esp_rom_sys.h" #include "soc/rtc_cntl_reg.h" -#if CONFIG_IDF_TARGET_ESP32C3 -#include "soc/syscon_reg.h" -#elif CONFIG_IDF_TARGET_ESP32S3 #include "soc/syscon_reg.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "soc/dport_reg.h" #endif #if CONFIG_IDF_TARGET_ESP32 @@ -279,9 +278,9 @@ void IRAM_ATTR esp_wifi_bt_power_domain_on(void) _lock_acquire(&s_wifi_bt_pd_controller.lock); if (s_wifi_bt_pd_controller.count++ == 0) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 - SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_WIFIBB_RST | SYSTEM_FE_RST); - CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_WIFIBB_RST | SYSTEM_FE_RST); +#if !CONFIG_IDF_TARGET_ESP32 + SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU); + CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU); #endif CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO); } diff --git a/components/esp_system/port/soc/esp32/system_internal.c b/components/esp_system/port/soc/esp32/system_internal.c index 432c44067b..072b7c8e94 100644 --- a/components/esp_system/port/soc/esp32/system_internal.c +++ b/components/esp_system/port/soc/esp32/system_internal.c @@ -110,11 +110,17 @@ void IRAM_ATTR esp_restart_noos(void) WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | - DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \ + DPORT_FE_RST | \ + DPORT_WIFIMAC_RST | \ + DPORT_BTBB_RST | \ + DPORT_BTMAC_RST | \ + DPORT_SDIO_RST | \ + DPORT_SDIO_HOST_RST | \ + DPORT_EMAC_RST | \ + DPORT_MACPWR_RST | \ + DPORT_RW_BTMAC_RST | \ + DPORT_RW_BTLP_RST); DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); // Reset timer/spi/uart diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c index 3df914bfec..2bbf681a44 100644 --- a/components/esp_system/port/soc/esp32s2/system_internal.c +++ b/components/esp_system/port/soc/esp32s2/system_internal.c @@ -98,11 +98,16 @@ void IRAM_ATTR esp_restart_noos(void) WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | - DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \ + DPORT_FE_RST | \ + DPORT_WIFIMAC_RST | \ + DPORT_BTBB_RST | \ + DPORT_BTMAC_RST | \ + DPORT_SDIO_RST | \ + DPORT_EMAC_RST | \ + DPORT_MACPWR_RST | \ + DPORT_RW_BTMAC_RST | \ + DPORT_RW_BTLP_RST); DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); // Reset timer/spi/uart diff --git a/components/hal/esp32/include/hal/clk_gate_ll.h b/components/hal/esp32/include/hal/clk_gate_ll.h index 834bb008b8..f8bcd3cd0c 100644 --- a/components/hal/esp32/include/hal/clk_gate_ll.h +++ b/components/hal/esp32/include/hal/clk_gate_ll.h @@ -105,7 +105,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en case PERIPH_LEDC_MODULE: return DPORT_LEDC_RST; case PERIPH_WIFI_MODULE: - return DPORT_MAC_RST; + return DPORT_WIFIMAC_RST; case PERIPH_UART0_MODULE: return DPORT_UART_RST; case PERIPH_UART1_MODULE: diff --git a/components/hal/esp32s2/include/hal/clk_gate_ll.h b/components/hal/esp32s2/include/hal/clk_gate_ll.h index eb5a47f955..a1ef5be97a 100644 --- a/components/hal/esp32s2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32s2/include/hal/clk_gate_ll.h @@ -98,7 +98,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en case PERIPH_LEDC_MODULE: return DPORT_LEDC_RST; case PERIPH_WIFI_MODULE: - return DPORT_MAC_RST; + return DPORT_WIFIMAC_RST; case PERIPH_UART0_MODULE: return DPORT_UART_RST; case PERIPH_UART1_MODULE: diff --git a/components/soc/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h index 367c9e43e0..5ace77ff83 100644 --- a/components/soc/esp32/include/soc/dport_reg.h +++ b/components/soc/esp32/include/soc/dport_reg.h @@ -1076,17 +1076,25 @@ #define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) /* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define DPORT_RW_BTLP_RST (BIT(10)) -#define DPORT_RW_BTMAC_RST (BIT(9)) -#define DPORT_MACPWR_RST (BIT(8)) -#define DPORT_EMAC_RST (BIT(7)) -#define DPORT_SDIO_HOST_RST (BIT(6)) -#define DPORT_SDIO_RST (BIT(5)) -#define DPORT_BTMAC_RST (BIT(4)) -#define DPORT_BT_RST (BIT(3)) -#define DPORT_MAC_RST (BIT(2)) -#define DPORT_FE_RST (BIT(1)) -#define DPORT_BB_RST (BIT(0)) +#define DPORT_WIFIBB_RST BIT(0) +#define DPORT_FE_RST BIT(1) +#define DPORT_WIFIMAC_RST BIT(2) +#define DPORT_BTBB_RST BIT(3) +#define DPORT_BTMAC_RST BIT(4) +#define DPORT_SDIO_RST BIT(5) +#define DPORT_SDIO_HOST_RST BIT(6) +#define DPORT_EMAC_RST BIT(7) +#define DPORT_MACPWR_RST BIT(8) +#define DPORT_RW_BTMAC_RST BIT(9) +#define DPORT_RW_BTLP_RST BIT(10) + +#define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \ + DPORT_FE_RST | \ + DPORT_WIFIMAC_RST | \ + DPORT_BTBB_RST | \ + DPORT_BTMAC_RST | \ + DPORT_RW_BTMAC_RST | \ + DPORT_RW_BTLP_RST) #define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) /* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ diff --git a/components/soc/esp32c3/include/soc/syscon_reg.h b/components/soc/esp32c3/include/soc/syscon_reg.h index c8719754d8..9514a644cb 100644 --- a/components/soc/esp32c3/include/soc/syscon_reg.h +++ b/components/soc/esp32c3/include/soc/syscon_reg.h @@ -193,6 +193,7 @@ extern "C" { #define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG #define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG + /* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define SYSTEM_WIFIBB_RST BIT(0) @@ -209,6 +210,17 @@ extern "C" { #define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */ #define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */ +#define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \ + SYSTEM_FE_RST | \ + SYSTEM_WIFIMAC_RST | \ + SYSTEM_BTBB_RST | \ + SYSTEM_BTMAC_RST | \ + SYSTEM_RW_BTMAC_RST | \ + SYSTEM_RW_BTLP_RST | \ + SYSTEM_RW_BTMAC_REG_RST | \ + SYSTEM_RW_BTLP_REG_RST | \ + SYSTEM_BTBB_REG_RST) + #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: */ diff --git a/components/soc/esp32s2/include/soc/syscon_reg.h b/components/soc/esp32s2/include/soc/syscon_reg.h index a0ab648a7b..bf7332412d 100644 --- a/components/soc/esp32s2/include/soc/syscon_reg.h +++ b/components/soc/esp32s2/include/soc/syscon_reg.h @@ -1,16 +1,8 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SYSCON_REG_H_ #define _SOC_SYSCON_REG_H_ @@ -469,23 +461,32 @@ extern "C" { #define DPORT_CORE_RST_EN_REG DPORT_WIFI_RST_EN_REG #define DPORT_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG + /* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define DPORT_WIFI_RST 0xFFFFFFFF #define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S)) #define DPORT_WIFI_RST_V 0xFFFFFFFF #define DPORT_WIFI_RST_S 0 -#define DPORT_RW_BTLP_RST (BIT(10)) -#define DPORT_RW_BTMAC_RST (BIT(9)) -#define DPORT_MACPWR_RST (BIT(8)) -#define DPORT_EMAC_RST (BIT(7)) -#define DPORT_SDIO_HOST_RST (BIT(6)) -#define DPORT_SDIO_RST (BIT(5)) -#define DPORT_BTMAC_RST (BIT(4)) -#define DPORT_BT_RST (BIT(3)) -#define DPORT_MAC_RST (BIT(2)) -#define DPORT_FE_RST (BIT(1)) -#define DPORT_BB_RST (BIT(0)) + +#define DPORT_WIFIBB_RST BIT(0) +#define DPORT_FE_RST BIT(1) +#define DPORT_WIFIMAC_RST BIT(2) +#define DPORT_BTBB_RST BIT(3) +#define DPORT_BTMAC_RST BIT(4) +#define DPORT_SDIO_RST BIT(5) +#define DPORT_EMAC_RST BIT(7) +#define DPORT_MACPWR_RST BIT(8) +#define DPORT_RW_BTMAC_RST BIT(9) +#define DPORT_RW_BTLP_RST BIT(10) + +#define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \ + DPORT_FE_RST | \ + DPORT_WIFIMAC_RST | \ + DPORT_BTBB_RST | \ + DPORT_BTMAC_RST | \ + DPORT_RW_BTMAC_RST | \ + DPORT_RW_BTLP_RST) #define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098) /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ diff --git a/components/soc/esp32s3/include/soc/syscon_reg.h b/components/soc/esp32s3/include/soc/syscon_reg.h index f3f08c1e4f..8412ca34c1 100644 --- a/components/soc/esp32s3/include/soc/syscon_reg.h +++ b/components/soc/esp32s3/include/soc/syscon_reg.h @@ -199,6 +199,7 @@ extern "C" { #define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S)) #define SYSTEM_WIFI_RST_V 0xFFFFFFFF #define SYSTEM_WIFI_RST_S 0 + #define SYSTEM_WIFIBB_RST BIT(0) #define SYSTEM_FE_RST BIT(1) #define SYSTEM_WIFIMAC_RST BIT(2) @@ -213,6 +214,17 @@ extern "C" { #define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */ #define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */ +#define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \ + SYSTEM_FE_RST | \ + SYSTEM_WIFIMAC_RST | \ + SYSTEM_BTBB_RST | \ + SYSTEM_BTMAC_RST | \ + SYSTEM_RW_BTMAC_RST | \ + SYSTEM_RW_BTLP_RST | \ + SYSTEM_RW_BTMAC_REG_RST | \ + SYSTEM_RW_BTLP_REG_RST | \ + SYSTEM_BTBB_REG_RST) + #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C) /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: .*/