diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c index efc420a776..20fb9fc1c0 100644 --- a/components/bootloader/src/main/bootloader_start.c +++ b/components/bootloader/src/main/bootloader_start.c @@ -18,6 +18,7 @@ #include "esp_attr.h" #include "esp_log.h" +#include "esp_dport_access.h" #include "rom/cache.h" #include "rom/efuse.h" @@ -90,9 +91,9 @@ void IRAM_ATTR call_start_cpu0() Cache_Flush(0); Cache_Flush(1); mmu_init(0); - REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); + DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); mmu_init(1); - REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); + DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); /* (above steps probably unnecessary for most serial bootloader usage, all that's absolutely needed is that we unmask DROM0 cache on the following two lines - normal ROM boot exits with @@ -103,8 +104,8 @@ void IRAM_ATTR call_start_cpu0() The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are necessary to work around a hardware bug. */ - REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0); - REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0); + DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0); + DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0); bootloader_main(); } @@ -579,8 +580,8 @@ static void set_cache_and_start_app( ESP_LOGV(TAG, "rc=%d", rc ); rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count ); ESP_LOGV(TAG, "rc=%d", rc ); - REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 ); - REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 ); + DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 ); + DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 ); Cache_Read_Enable( 0 ); // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) @@ -768,10 +769,10 @@ static void uart_console_configure(void) static void wdt_reset_info_enable(void) { - REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE); - REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE); - REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE); - REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE); + DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE); + DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE); + DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE); + DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE); } static void wdt_reset_info_dump(int cpu) @@ -781,26 +782,26 @@ static void wdt_reset_info_dump(int cpu) char *cpu_name = cpu ? "APP" : "PRO"; if (cpu == 0) { - stat = REG_READ(DPORT_PRO_CPU_RECORD_STATUS_REG); - pid = REG_READ(DPORT_PRO_CPU_RECORD_PID_REG); - inst = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGINST_REG); - dstat = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG); - data = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG); - pc = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGPC_REG); - lsstat = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG); - lsaddr = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG); - lsdata = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG); + stat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_STATUS_REG); + pid = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PID_REG); + inst = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGINST_REG); + dstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG); + data = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG); + pc = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGPC_REG); + lsstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG); + lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG); + lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG); } else { - stat = REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG); - pid = REG_READ(DPORT_APP_CPU_RECORD_PID_REG); - inst = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG); - dstat = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG); - data = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGDATA_REG); - pc = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGPC_REG); - lsstat = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG); - lsaddr = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG); - lsdata = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG); + stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG); + pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG); + inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG); + dstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG); + data = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGDATA_REG); + pc = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGPC_REG); + lsstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG); + lsaddr = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG); + lsdata = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG); } if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 && DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) { diff --git a/components/bootloader_support/src/bootloader_random.c b/components/bootloader_support/src/bootloader_random.c index fe5a019f84..480f603e64 100644 --- a/components/bootloader_support/src/bootloader_random.c +++ b/components/bootloader_support/src/bootloader_random.c @@ -20,6 +20,7 @@ #include "soc/dport_reg.h" #include "soc/i2s_reg.h" #include "esp_log.h" +#include "esp_dport_access.h" #ifndef BOOTLOADER_BUILD #include "esp_system.h" @@ -65,7 +66,7 @@ void bootloader_random_enable(void) /* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is never disabled while the CPU is running), this is a "belts and braces" type check. */ - SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN); + DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN); /* Enable SAR ADC in test mode to feed ADC readings of the 1.1V reference via I2S into the RNG entropy input. @@ -77,7 +78,7 @@ void bootloader_random_enable(void) SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP); CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP); // Test pattern configuration byte 0xAD: @@ -115,7 +116,7 @@ void bootloader_random_enable(void) void bootloader_random_disable(void) { /* Disable i2s clock */ - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); /* Reset some i2s configuration (possibly redundant as we reset entire @@ -138,8 +139,8 @@ void bootloader_random_disable(void) SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S); /* Reset i2s peripheral */ - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); /* Disable pull supply voltage to SAR ADC */ CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); diff --git a/components/driver/periph_ctrl.c b/components/driver/periph_ctrl.c index d90fa595f9..7615d94abd 100644 --- a/components/driver/periph_ctrl.c +++ b/components/driver/periph_ctrl.c @@ -13,6 +13,7 @@ // limitations under the License. #include #include "esp_intr.h" +#include "esp_dport_access.h" #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "freertos/xtensa_api.h" @@ -26,88 +27,88 @@ void periph_module_enable(periph_module_t periph) portENTER_CRITICAL(&periph_spinlock); switch(periph) { case PERIPH_RMT_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_RMT_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_RMT_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST); break; case PERIPH_LEDC_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); break; case PERIPH_UART0_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST); break; case PERIPH_UART1_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST); break; case PERIPH_UART2_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST); break; case PERIPH_I2C0_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST); break; case PERIPH_I2C1_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT1_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST); break; case PERIPH_I2S0_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); break; case PERIPH_I2S1_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST); break; case PERIPH_TIMG0_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); break; case PERIPH_TIMG1_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); break; case PERIPH_PWM0_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST); break; case PERIPH_PWM1_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST); break; case PERIPH_PWM2_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST); break; case PERIPH_PWM3_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST); break; case PERIPH_UHCI0_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST); break; case PERIPH_UHCI1_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST); break; case PERIPH_PCNT_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PCNT_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PCNT_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST); break; case PERIPH_SPI_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1); break; case PERIPH_HSPI_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST); break; case PERIPH_VSPI_MODULE: - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2); break; default: break; @@ -120,88 +121,88 @@ void periph_module_disable(periph_module_t periph) portENTER_CRITICAL(&periph_spinlock); switch(periph) { case PERIPH_RMT_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_RMT_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_RMT_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST); break; case PERIPH_LEDC_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); break; case PERIPH_UART0_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST); break; case PERIPH_UART1_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST); break; case PERIPH_UART2_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST); break; case PERIPH_I2C0_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST); break; case PERIPH_I2C1_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST); break; case PERIPH_I2S0_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); break; case PERIPH_I2S1_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST); break; case PERIPH_TIMG0_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); break; case PERIPH_TIMG1_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); break; case PERIPH_PWM0_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST); break; case PERIPH_PWM1_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST); break; case PERIPH_PWM2_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST); break; case PERIPH_PWM3_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST); break; case PERIPH_UHCI0_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST); break; case PERIPH_UHCI1_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST); break; case PERIPH_PCNT_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PCNT_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PCNT_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST); break; case PERIPH_SPI_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1); break; case PERIPH_HSPI_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST); break; case PERIPH_VSPI_MODULE: - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2); - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2); break; default: break; diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index d58d202d31..14cb9c661b 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -24,6 +24,7 @@ #include "esp_attr.h" #include "esp_intr.h" #include "esp_intr_alloc.h" +#include "esp_dport_access.h" #include "esp_log.h" #include "esp_err.h" #include "soc/soc.h" @@ -252,7 +253,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf } //Select DMA channel. - SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2)); + DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2)); return ESP_OK; } @@ -358,8 +359,8 @@ bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t ret = false; } else { //Reset DMA - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); ret = true; } portEXIT_CRITICAL(&dmaworkaround_mux); @@ -377,8 +378,8 @@ void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan) dmaworkaround_channels_busy[dmachan] = 0; if (dmaworkaround_waiting_for_chan == dmachan) { //Reset DMA - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); dmaworkaround_waiting_for_chan = 0; //Call callback dmaworkaround_cb(dmaworkaround_cb_arg); diff --git a/components/esp32/app_trace.c b/components/esp32/app_trace.c index 47b7a021ea..18a12f8589 100644 --- a/components/esp32/app_trace.c +++ b/components/esp32/app_trace.c @@ -149,6 +149,7 @@ #include "soc/timer_group_struct.h" #include "soc/timer_group_reg.h" #include "esp_app_trace.h" +#include "esp_dport_access.h" #if CONFIG_ESP32_APPTRACE_ENABLE #define ESP_APPTRACE_DEBUG_STATS_ENABLE 0 @@ -594,7 +595,7 @@ static esp_err_t esp_apptrace_trax_block_switch() // switch to new block s_trace_buf.trax.state.in_block++; - WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, new_block_num ? TRACEMEM_MUX_BLK0_ONLY : TRACEMEM_MUX_BLK1_ONLY); + DPORT_WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, new_block_num ? TRACEMEM_MUX_BLK0_ONLY : TRACEMEM_MUX_BLK1_ONLY); eri_write(ESP_APPTRACE_TRAX_CTRL_REG, ESP_APPTRACE_TRAX_BLOCK_ID(s_trace_buf.trax.state.in_block) | host_connected | ESP_APPTRACE_TRAX_BLOCK_LEN(s_trace_buf.trax.state.markers[prev_block_num])); @@ -736,12 +737,12 @@ static esp_err_t esp_apptrace_trax_dest_init() } s_trace_buf.trax.state.in_block = ESP_APPTRACE_TRAX_INBLOCK_START; - WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, DPORT_PRO_TRACEMEM_ENA_M); + DPORT_WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, DPORT_PRO_TRACEMEM_ENA_M); #if CONFIG_FREERTOS_UNICORE == 0 - WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_M); + DPORT_WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_M); #endif // Expose block 1 to host, block 0 is current trace input buffer - WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK1_ONLY); + DPORT_WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK1_ONLY); return ESP_OK; } diff --git a/components/esp32/cache_err_int.c b/components/esp32/cache_err_int.c index ece6c2d604..8fd1f009e8 100644 --- a/components/esp32/cache_err_int.c +++ b/components/esp32/cache_err_int.c @@ -27,6 +27,7 @@ #include "esp_err.h" #include "esp_intr.h" #include "esp_attr.h" +#include "esp_dport_access.h" #include "soc/dport_reg.h" #include "sdkconfig.h" @@ -51,7 +52,7 @@ void esp_cache_err_int_init() // CPU. if (core_id == PRO_CPU_NUM) { - SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG, + DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG, DPORT_CACHE_IA_INT_PRO_OPPOSITE | DPORT_CACHE_IA_INT_PRO_DRAM1 | DPORT_CACHE_IA_INT_PRO_DROM0 | @@ -59,7 +60,7 @@ void esp_cache_err_int_init() DPORT_CACHE_IA_INT_PRO_IRAM0 | DPORT_CACHE_IA_INT_PRO_IRAM1); } else { - SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG, + DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG, DPORT_CACHE_IA_INT_APP_OPPOSITE | DPORT_CACHE_IA_INT_APP_DRAM1 | DPORT_CACHE_IA_INT_APP_DROM0 | @@ -80,7 +81,7 @@ int IRAM_ATTR esp_cache_err_get_cpuid() DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 | DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE; - if (GET_PERI_REG_MASK(DPORT_PRO_DCACHE_DBUG3_REG, pro_mask)) { + if (DPORT_GET_PERI_REG_MASK(DPORT_PRO_DCACHE_DBUG3_REG, pro_mask)) { return PRO_CPU_NUM; } @@ -92,7 +93,7 @@ int IRAM_ATTR esp_cache_err_get_cpuid() DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 | DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE; - if (GET_PERI_REG_MASK(DPORT_APP_DCACHE_DBUG3_REG, app_mask)) { + if (DPORT_GET_PERI_REG_MASK(DPORT_APP_DCACHE_DBUG3_REG, app_mask)) { return APP_CPU_NUM; } return -1; diff --git a/components/esp32/component.mk b/components/esp32/component.mk index c7be4bb039..aef14ab3cc 100644 --- a/components/esp32/component.mk +++ b/components/esp32/component.mk @@ -2,6 +2,10 @@ # Component Makefile # +#ifdef IS_BOOTLOADER_BUILD +CFLAGS += -DBOOTLOADER_BUILD +#endif + COMPONENT_SRCDIRS := . hwcrypto LIBS := core rtc ifdef CONFIG_PHY_ENABLED # BT || WIFI diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c index 86df9ca4d9..e98a86b38e 100644 --- a/components/esp32/cpu_start.c +++ b/components/esp32/cpu_start.c @@ -49,6 +49,7 @@ #include "esp_spi_flash.h" #include "esp_ipc.h" #include "esp_crosscore_int.h" +#include "esp_dport_access.h" #include "esp_log.h" #include "esp_vfs_dev.h" #include "esp_newlib.h" @@ -142,10 +143,10 @@ void IRAM_ATTR call_start_cpu0() Cache_Read_Enable(1); esp_cpu_unstall(1); //Enable clock gating and reset the app cpu. - SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); - CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL); - SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); - CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); + DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL); + DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); + DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1); while (!app_cpu_started) { @@ -153,7 +154,7 @@ void IRAM_ATTR call_start_cpu0() } #else ESP_EARLY_LOGI(TAG, "Single core mode"); - CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); #endif /* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted. @@ -242,6 +243,9 @@ void start_cpu0_default(void) esp_cache_err_int_init(); esp_crosscore_int_init(); esp_ipc_init(); +#ifndef CONFIG_FREERTOS_UNICORE + esp_dport_access_int_init(); +#endif spi_flash_init(); /* init default OS-aware flash access critical section */ spi_flash_guard_set(&g_flash_guard_default_ops); @@ -277,6 +281,7 @@ void start_cpu1_default(void) //has started, but it isn't active *on this CPU* yet. esp_cache_err_int_init(); esp_crosscore_int_init(); + esp_dport_access_int_init(); ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU."); xPortStartScheduler(); diff --git a/components/esp32/crosscore_int.c b/components/esp32/crosscore_int.c index f75f0eba7d..27fb9887fe 100644 --- a/components/esp32/crosscore_int.c +++ b/components/esp32/crosscore_int.c @@ -18,6 +18,7 @@ #include "esp_err.h" #include "esp_intr.h" #include "esp_intr_alloc.h" +#include "esp_dport_access.h" #include "rom/ets_sys.h" #include "rom/uart.h" @@ -51,9 +52,9 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) { //Clear the interrupt first. if (xPortGetCoreID()==0) { - WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0); + DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0); } else { - WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0); + DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0); } //Grab the reason and clear it. portENTER_CRITICAL(&reasonSpinlock); @@ -90,9 +91,9 @@ void IRAM_ATTR esp_crosscore_int_send_yield(int coreId) { portEXIT_CRITICAL(&reasonSpinlock); //Poke the other CPU. if (coreId==0) { - WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0); + DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0); } else { - WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1); + DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1); } } diff --git a/components/esp32/deep_sleep.c b/components/esp32/deep_sleep.c index 6f7e3b24c7..d13b8d556e 100644 --- a/components/esp32/deep_sleep.c +++ b/components/esp32/deep_sleep.c @@ -16,6 +16,7 @@ #include #include "esp_attr.h" #include "esp_deep_sleep.h" +#include "esp_dport_access.h" #include "esp_log.h" #include "esp_clk.h" #include "rom/cache.h" @@ -90,8 +91,8 @@ void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub) void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) { /* Clear MMU for CPU 0 */ - REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR); - REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR); + DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR); + DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR); #if CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0 // ROM code has not started yet, so we need to set delay factor // used by ets_delay_us first. diff --git a/components/esp32/dport_access.c b/components/esp32/dport_access.c new file mode 100644 index 0000000000..3d45debef0 --- /dev/null +++ b/components/esp32/dport_access.c @@ -0,0 +1,182 @@ +// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* + * DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously + * This function will be initialize after FreeRTOS startup. + * When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt, + * cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt. + */ + +#include +#include + +#include "esp_attr.h" +#include "esp_err.h" +#include "esp_intr.h" +#include "esp_dport_access.h" +#include "rom/ets_sys.h" +#include "rom/uart.h" + +#include "soc/cpu.h" +#include "soc/dport_reg.h" +#include "soc/spi_reg.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "freertos/queue.h" +#include "freertos/portmacro.h" + +#include "xtensa/core-macros.h" + +static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED; + +#define DPORT_CORE_STATE_IDLE 0 +#define DPORT_CORE_STATE_RUNNING 1 +static uint32_t volatile dport_core_state[portNUM_PROCESSORS]; //cpu is already run + +/* these global variables are accessed from interrupt vector, hence not declared as static */ +uint32_t volatile dport_access_start[portNUM_PROCESSORS]; //dport register could be accessed +uint32_t volatile dport_access_end[portNUM_PROCESSORS]; //dport register is accessed over + +static uint32_t volatile dport_access_ref[portNUM_PROCESSORS]; //dport access reference + +#ifdef DPORT_ACCESS_BENCHMARK +#define DPORT_ACCESS_BENCHMARK_STORE_NUM +static uint32_t ccount_start[portNUM_PROCESSORS]; +static uint32_t ccount_end[portNUM_PROCESSORS]; +static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_NUM]; +static uint32_t ccount_margin_cnt; +#endif + +/* stall other cpu that this cpu is pending to access dport register start */ +void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void) +{ +#ifndef CONFIG_FREERTOS_UNICORE + int cpu_id = xPortGetCoreID(); + + if (dport_core_state[0] == DPORT_CORE_STATE_IDLE + || dport_core_state[1] == DPORT_CORE_STATE_IDLE) { + return; + } + +#ifdef DPORT_ACCESS_BENCHMARK + ccount_start[cpu_id] = XTHAL_GET_CCOUNT(); +#endif + + portDISABLE_INTERRUPTS(); + + if (dport_access_ref[cpu_id] == 0) { + portENTER_CRITICAL_ISR(&g_dport_mux); + + dport_access_start[cpu_id] = 0; + dport_access_end[cpu_id] = 0; + + if (cpu_id == 0) { + WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1 + } else { + WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0 + } + + while (!dport_access_start[cpu_id]) {}; + + REG_READ(SPI_DATE_REG(3)); //just read a APB register sure that the APB-bus is idle + } + + dport_access_ref[cpu_id]++; +#endif /* CONFIG_FREERTOS_UNICORE */ +} + +/* stall other cpu that this cpu is pending to access dport register end */ +void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void) +{ +#ifndef CONFIG_FREERTOS_UNICORE + int cpu_id = xPortGetCoreID(); + + if (dport_core_state[0] == DPORT_CORE_STATE_IDLE + || dport_core_state[1] == DPORT_CORE_STATE_IDLE) { + return; + } + + if (dport_access_ref[cpu_id] == 0) { + assert(0); + } + + dport_access_ref[cpu_id]--; + + if (dport_access_ref[cpu_id] == 0) { + dport_access_end[cpu_id] = 1; + + portEXIT_CRITICAL_ISR(&g_dport_mux); + } + + portENABLE_INTERRUPTS(); + +#ifdef DPORT_ACCESS_BENCHMARK + ccount_end[cpu_id] = XTHAL_GET_CCOUNT(); + ccount_margin[cpu_id][ccount_margin_cnt] = ccount_end[cpu_id] - ccount_start[cpu_id]; + ccount_margin_cnt = (ccount_margin_cnt + 1)&(DPORT_ACCESS_BENCHMARK_STORE_NUM - 1); +#endif +#endif /* CONFIG_FREERTOS_UNICORE */ +} + +static void dport_access_init_core0(void *arg) +{ + int core_id = xPortGetCoreID(); + + assert(core_id == 0); + + vPortCPUInitializeMutex(&g_dport_mux); + + ESP_INTR_DISABLE(ETS_DPORT_INUM); + intr_matrix_set(core_id, ETS_FROM_CPU_INTR2_SOURCE, ETS_DPORT_INUM); + ESP_INTR_ENABLE(ETS_DPORT_INUM); + + dport_access_ref[core_id] = 0; + dport_access_start[core_id] = 0; + dport_access_end[core_id] = 0; + dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING; + + vTaskDelete(NULL); +} + +static void dport_access_init_core1(void *arg) +{ + int core_id = xPortGetCoreID(); + + assert(core_id == 1); + + ESP_INTR_DISABLE(ETS_DPORT_INUM); + intr_matrix_set(core_id, ETS_FROM_CPU_INTR3_SOURCE, ETS_DPORT_INUM); + ESP_INTR_ENABLE(ETS_DPORT_INUM); + + dport_access_ref[core_id] = 0; + dport_access_start[core_id] = 0; + dport_access_end[core_id] = 0; + dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING; + + vTaskDelete(NULL); +} + + +/* This initialise should be really effective after vTaskStartScheduler */ +void esp_dport_access_int_init(void) +{ + if (xPortGetCoreID() == 0) { + xTaskCreatePinnedToCore(&dport_access_init_core0, "dport0", 512, NULL, 5, NULL, 0); + } else { + xTaskCreatePinnedToCore(&dport_access_init_core1, "dport1", 512, NULL, 5, NULL, 1); + } +} diff --git a/components/esp32/hwcrypto/aes.c b/components/esp32/hwcrypto/aes.c index 8f27cd17c2..74f87d9a7b 100644 --- a/components/esp32/hwcrypto/aes.c +++ b/components/esp32/hwcrypto/aes.c @@ -29,6 +29,7 @@ #include "hwcrypto/aes.h" #include "rom/aes.h" #include "soc/dport_reg.h" +#include "esp_dport_access.h" #include static _lock_t aes_lock; @@ -38,10 +39,10 @@ void esp_aes_acquire_hardware( void ) /* newlib locks lazy initialize on ESP-IDF */ _lock_acquire(&aes_lock); /* Enable AES hardware */ - REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES); + DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES); /* Clear reset on digital signature & secure boot units, otherwise AES unit is held in reset also. */ - REG_CLR_BIT(DPORT_PERI_RST_EN_REG, + DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_AES | DPORT_PERI_EN_DIGITAL_SIGNATURE | DPORT_PERI_EN_SECUREBOOT); @@ -50,10 +51,10 @@ void esp_aes_acquire_hardware( void ) void esp_aes_release_hardware( void ) { /* Disable AES hardware */ - REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_AES); + DPORT_REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_AES); /* Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively. */ - REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES); + DPORT_REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES); _lock_release(&aes_lock); } diff --git a/components/esp32/hwcrypto/sha.c b/components/esp32/hwcrypto/sha.c index 61e37b01d2..e7de230843 100644 --- a/components/esp32/hwcrypto/sha.c +++ b/components/esp32/hwcrypto/sha.c @@ -35,6 +35,7 @@ #include "rom/ets_sys.h" #include "soc/dport_reg.h" #include "soc/hwcrypto_reg.h" +#include "esp_dport_access.h" inline static uint32_t SHA_LOAD_REG(esp_sha_type sha_type) { return SHA_1_LOAD_REG + sha_type * 0x10; @@ -160,9 +161,9 @@ static void esp_sha_lock_engine_inner(sha_engine_state *engine) if (sha_engines_all_idle()) { /* Enable SHA hardware */ - REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_SHA); + DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_SHA); /* also clear reset on secure boot, otherwise SHA is held in reset */ - REG_CLR_BIT(DPORT_PERI_RST_EN_REG, + DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_SHA | DPORT_PERI_EN_SECUREBOOT); ets_sha_enable(); @@ -187,8 +188,8 @@ void esp_sha_unlock_engine(esp_sha_type sha_type) if (sha_engines_all_idle()) { /* Disable SHA hardware */ /* Don't assert reset on secure boot, otherwise AES is held in reset */ - REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_SHA); - REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_SHA); + DPORT_REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_SHA); + DPORT_REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_SHA); } _lock_release(&state_change_lock); diff --git a/components/esp32/include/esp_dport_access.h b/components/esp32/include/esp_dport_access.h new file mode 100644 index 0000000000..a7ce266690 --- /dev/null +++ b/components/esp32/include/esp_dport_access.h @@ -0,0 +1,109 @@ +// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_DPORT_ACCESS_H_ +#define _ESP_DPORT_ACCESS_H_ + +#include + +void esp_dport_access_stall_other_cpu_start(void); +void esp_dport_access_stall_other_cpu_end(void); +void esp_dport_access_int_init(void); + +#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) +#define DPORT_STAL_OTHER_CPU_START() +#define DPORT_STAL_OTHER_CPU_END() +#else +#define DPORT_STAL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start() +#define DPORT_STAL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end() +#endif + +#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DPORT_DATE_REG) + +//Registers Operation {{ + +#define _REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) +#define _REG_READ(_r) (*(volatile uint32_t *)(_r)) +//write value to register +#define DPORT_REG_WRITE(_r, _v) {DPORT_STAL_OTHER_CPU_START(); (*(volatile uint32_t *)(_r)) = (_v); DPORT_STAL_OTHER_CPU_END();} + +//read value from register +#define DPORT_REG_READ(_r) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = (*(volatile uint32_t *)(_r)); DPORT_STAL_OTHER_CPU_END(); val;}) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = (*(volatile uint32_t*)(_r) & (_b)); DPORT_STAL_OTHER_CPU_END(); val;}) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) {DPORT_STAL_OTHER_CPU_START(); (*(volatile uint32_t*)(_r) |= (_b)); DPORT_STAL_OTHER_CPU_END();} + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) {DPORT_STAL_OTHER_CPU_START(); (*(volatile uint32_t*)(_r) &= ~(_b)); DPORT_STAL_OTHER_CPU_END();} + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) {DPORT_STAL_OTHER_CPU_START(); (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); DPORT_STAL_OTHER_CPU_END();} + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = ((_REG_READ(_r) >> (_f##_S)) & (_f##_V)); DPORT_STAL_OTHER_CPU_END(); val;}) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) {DPORT_STAL_OTHER_CPU_START(); (_REG_WRITE((_r),((_REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S))))); DPORT_STAL_OTHER_CPU_END();} + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = (((_r) >> (_f##_S)) & (_f)); DPORT_STAL_OTHER_CPU_END(); val;}) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = (((_r) & (_f))>> (_f##_S)); DPORT_STAL_OTHER_CPU_END(); val;}) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) {DPORT_STAL_OTHER_CPU_START(); ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))); DPORT_STAL_OTHER_CPU_END();} + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) {DPORT_STAL_OTHER_CPU_START(); ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))); DPORT_STAL_OTHER_CPU_END();} + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = (((_v)&(_f))<<_f##_S); DPORT_STAL_OTHER_CPU_END(); val;}) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = (((_v)<<_f##_S) & (_f)); DPORT_STAL_OTHER_CPU_END(); val;}) + +#define _READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) +#define _WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) + +//read value from register +#define DPORT_READ_PERI_REG(addr) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); DPORT_STAL_OTHER_CPU_END(); val;}) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) {DPORT_STAL_OTHER_CPU_START(); (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); DPORT_STAL_OTHER_CPU_END();} + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) {DPORT_STAL_OTHER_CPU_START(); _WRITE_PERI_REG((reg), (_READ_PERI_REG(reg)&(~(mask)))); DPORT_STAL_OTHER_CPU_END();} + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) {DPORT_STAL_OTHER_CPU_START(); _WRITE_PERI_REG((reg), (_READ_PERI_REG(reg)|(mask))); DPORT_STAL_OTHER_CPU_END();} + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = (_READ_PERI_REG(reg) & (mask)); DPORT_STAL_OTHER_CPU_END(); val;}) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = ((_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); DPORT_STAL_OTHER_CPU_END(); val;}) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) {DPORT_STAL_OTHER_CPU_START(); (_WRITE_PERI_REG((reg),(_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); DPORT_STAL_OTHER_CPU_END();} + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ({uint32_t val; DPORT_STAL_OTHER_CPU_START(); val = ((_READ_PERI_REG(reg)>>(shift))&(mask)); DPORT_STAL_OTHER_CPU_END(); val;}) +//}} + + +#endif /* _ESP_DPORT_ACCESS_H_ */ diff --git a/components/esp32/phy_init.c b/components/esp32/phy_init.c index 0718079247..5d616deb80 100644 --- a/components/esp32/phy_init.c +++ b/components/esp32/phy_init.c @@ -26,6 +26,7 @@ #include "esp_err.h" #include "esp_phy_init.h" +#include "esp_dport_access.h" #include "esp_system.h" #include "esp_log.h" #include "nvs.h" @@ -52,7 +53,7 @@ esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data, _lock_acquire(&s_phy_rf_init_lock); if (s_phy_rf_init_count == 0) { // Enable WiFi peripheral clock - SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN | DPORT_WIFI_CLK_RNG_EN); + DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN | DPORT_WIFI_CLK_RNG_EN); ESP_LOGV(TAG, "register_chipv7_phy, init_data=%p, cal_data=%p, mode=%d", init_data, calibration_data, mode); phy_set_wifi_mode_only(0); @@ -77,7 +78,7 @@ esp_err_t esp_phy_rf_deinit(void) // Disable PHY and RF. phy_close_rf(); // Disable WiFi peripheral clock. Do not disable clock for hardware RNG - CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN); } else { #if CONFIG_SW_COEXIST_ENABLE coex_deinit(); diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c index ab271063e6..9f2aad8bb8 100644 --- a/components/esp32/system_api.c +++ b/components/esp32/system_api.c @@ -19,6 +19,7 @@ #include "esp_wifi.h" #include "esp_wifi_internal.h" #include "esp_log.h" +#include "esp_dport_access.h" #include "sdkconfig.h" #include "rom/efuse.h" #include "rom/cache.h" @@ -270,17 +271,17 @@ void IRAM_ATTR esp_restart_noos() uart_tx_wait_idle(2); // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - REG_WRITE(DPORT_CORE_RST_EN_REG, 0); + DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); // Reset timer/spi/uart - SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERS_RST | DPORT_SPI_RST_1 | DPORT_UART_RST); - REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); + DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Set CPU back to XTAL source, no PLL, same as hard reset rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); diff --git a/components/esp32/test/test_ahb_arb.c b/components/esp32/test/test_ahb_arb.c index 21cf6d7781..43b138c561 100644 --- a/components/esp32/test/test_ahb_arb.c +++ b/components/esp32/test/test_ahb_arb.c @@ -21,6 +21,8 @@ #include "soc/gpio_reg.h" #include "soc/i2s_reg.h" +#include "esp_dport_access.h" + #define DPORT_I2S0_CLK_EN (BIT(4)) #define DPORT_I2S0_RST (BIT(4)) @@ -34,8 +36,8 @@ the point where they happened to do what I want. static void lcdIfaceInit() { - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); //Init pins to i2s functions SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable diff --git a/components/esp32/test/test_unal_dma.c b/components/esp32/test/test_unal_dma.c index c05d0d0f36..948f35e29f 100644 --- a/components/esp32/test/test_unal_dma.c +++ b/components/esp32/test/test_unal_dma.c @@ -21,6 +21,7 @@ #include "soc/gpio_reg.h" #include "soc/i2s_reg.h" +#include "esp_dport_access.h" #define DPORT_I2S0_CLK_EN (BIT(4)) #define DPORT_I2S0_RST (BIT(4)) @@ -32,8 +33,8 @@ static volatile lldesc_t dmaDesc[2]; static void dmaMemcpy(void *in, void *out, int len) { volatile int i; - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); //Init pins to i2s functions SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable diff --git a/components/freertos/test/test_freertos.c b/components/freertos/test/test_freertos.c index 2eb0c9391b..e85037b020 100644 --- a/components/freertos/test/test_freertos.c +++ b/components/freertos/test/test_freertos.c @@ -15,6 +15,7 @@ #include "soc/uart_reg.h" #include "soc/dport_reg.h" #include "soc/io_mux_reg.h" +#include "esp_dport_access.h" void ets_isr_unmask(uint32_t unmask); @@ -178,8 +179,8 @@ static void uartRxInit(xQueueHandle q) SET_PERI_REG_MASK(UART_INT_ENA_REG(0), UART_RXFIFO_FULL_INT_ENA); printf("Enabling int %d\n", ETS_UART0_INUM); - REG_SET_FIELD(DPORT_PRO_UART_INTR_MAP_REG, DPORT_PRO_UART_INTR_MAP, ETS_UART0_INUM); - REG_SET_FIELD(DPORT_PRO_UART1_INTR_MAP_REG, DPORT_PRO_UART1_INTR_MAP, ETS_UART0_INUM); + DPORT_REG_SET_FIELD(DPORT_PRO_UART_INTR_MAP_REG, DPORT_PRO_UART_INTR_MAP, ETS_UART0_INUM); + DPORT_REG_SET_FIELD(DPORT_PRO_UART1_INTR_MAP_REG, DPORT_PRO_UART1_INTR_MAP, ETS_UART0_INUM); xt_set_interrupt_handler(ETS_UART0_INUM, uartIsrHdl, NULL); xt_ints_on(1 << ETS_UART0_INUM); diff --git a/components/freertos/test/test_ringbuf.c b/components/freertos/test/test_ringbuf.c index 8f8328532d..32798a00f5 100644 --- a/components/freertos/test/test_ringbuf.c +++ b/components/freertos/test/test_ringbuf.c @@ -16,6 +16,7 @@ #include "soc/uart_reg.h" #include "soc/dport_reg.h" #include "soc/io_mux_reg.h" +#include "esp_dport_access.h" #include #include @@ -150,8 +151,8 @@ static void uartRxInit() SET_PERI_REG_MASK(UART_INT_ENA_REG(0), UART_RXFIFO_FULL_INT_ENA); printf("Enabling int %d\n", ETS_UART0_INUM); - REG_SET_FIELD(DPORT_PRO_UART_INTR_MAP_REG, DPORT_PRO_UART_INTR_MAP, ETS_UART0_INUM); - REG_SET_FIELD(DPORT_PRO_UART1_INTR_MAP_REG, DPORT_PRO_UART1_INTR_MAP, ETS_UART0_INUM); + DPORT_REG_SET_FIELD(DPORT_PRO_UART_INTR_MAP_REG, DPORT_PRO_UART_INTR_MAP, ETS_UART0_INUM); + DPORT_REG_SET_FIELD(DPORT_PRO_UART1_INTR_MAP_REG, DPORT_PRO_UART1_INTR_MAP, ETS_UART0_INUM); xt_set_interrupt_handler(ETS_UART0_INUM, uartIsrHdl, NULL); xt_ints_on(1 << ETS_UART0_INUM); diff --git a/components/freertos/xtensa_vectors.S b/components/freertos/xtensa_vectors.S index ffbdb51407..a6dd01d315 100644 --- a/components/freertos/xtensa_vectors.S +++ b/components/freertos/xtensa_vectors.S @@ -94,6 +94,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "esp_panic.h" #include "sdkconfig.h" #include "soc/soc.h" +#include "soc/dport_reg.h" + /* Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used. Please change this when the tcb structure is changed @@ -1709,7 +1711,7 @@ _xt_highint4: l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ wsr a0, PS l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ - wsr a0, EPC_1 + wsr a0, EPC_4 l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ l32i sp, sp, XT_STK_A1 /* remove exception frame */ rsync /* ensure PS and EPC written */ @@ -1733,6 +1735,13 @@ _Level5Vector: .end literal_prefix +#define L5_INTR_STACK_SIZE 8 +#define L5_INTR_A2_OFFSET 0 +#define L5_INTR_A3_OFFSET 4 + .data +_l5_intr_stack: + .space L5_INTR_STACK_SIZE + .section .iram1,"ax" .type _xt_highint5,@function .align 4 @@ -1748,9 +1757,60 @@ _xt_highint5: 1: #endif - /* USER_EDIT: - ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. - */ + /* This section is for access dport register protection */ + /* Allocate exception frame and save minimal context. */ + /* Because the interrupt cause code have protection that only + allow one cpu enter in L5 interrupt at one time, so + there needn't have two _l5_intr_stack for each cpu */ + + movi a0, _l5_intr_stack + s32i a2, a0, L5_INTR_A2_OFFSET + s32i a3, a0, L5_INTR_A3_OFFSET + + /* Check interrupt */ + rsr a0, INTERRUPT + extui a0, a0, ETS_DPORT_INUM, 1 /* get dport int bit */ + beqz a0, 1f + + /* handle dport interrupt */ + /* get CORE_ID */ + getcoreid a0 + beqz a0, 2f + + /* current cpu is 1 */ + movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG + movi a2, 0 + s32i a2, a0, 0 /* clear intr */ + movi a0, 0 /* other cpu id */ + j 3f +2: + /* current cpu is 0 */ + movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG + movi a2, 0 + s32i a2, a0, 0 /* clear intr */ + movi a0, 1 /* other cpu id */ +3: + /* set and wait flag */ + movi a2, dport_access_start + addx4 a2, a0, a2 + movi a3, 1 + s32i a3, a2, 0 + memw + movi a2, dport_access_end + addx4 a2, a0, a2 +.check_dport_access_end: + l32i a3, a2, 0 + beqz a3, .check_dport_access_end + +1: + movi a0, _l5_intr_stack + l32i a2, a0, L5_INTR_A2_OFFSET + l32i a3, a0, L5_INTR_A3_OFFSET + rsync /* ensure register restored */ + + rsr a0, EXCSAVE_5 /* restore a0 */ + rfi 5 + .align 4 .L_xt_highint5_exit: diff --git a/components/mbedtls/port/esp_bignum.c b/components/mbedtls/port/esp_bignum.c index 1dd7ea447e..bfc1a8fa9c 100644 --- a/components/mbedtls/port/esp_bignum.c +++ b/components/mbedtls/port/esp_bignum.c @@ -34,6 +34,7 @@ #include "esp_intr.h" #include "esp_intr_alloc.h" #include "esp_attr.h" +#include "esp_dport_access.h" #include "soc/dport_reg.h" @@ -76,13 +77,13 @@ void esp_mpi_acquire_hardware( void ) /* newlib locks lazy initialize on ESP-IDF */ _lock_acquire(&mpi_lock); - REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA); + DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA); /* also clear reset on digital signature, otherwise RSA is held in reset */ - REG_CLR_BIT(DPORT_PERI_RST_EN_REG, + DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_RSA | DPORT_PERI_EN_DIGITAL_SIGNATURE); - REG_CLR_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD); + DPORT_REG_CLR_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD); while(REG_READ(RSA_CLEAN_REG) != 1); @@ -95,11 +96,11 @@ void esp_mpi_acquire_hardware( void ) void esp_mpi_release_hardware( void ) { - REG_SET_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD); + DPORT_REG_SET_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD); /* don't reset digital signature unit, as this resets AES also */ - REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_RSA); - REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA); + DPORT_REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_RSA); + DPORT_REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA); _lock_release(&mpi_lock); } diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 1df888ce7c..fa99d9131d 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -238,8 +238,8 @@ #define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/ #define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ #define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ -#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for VHCI */ -#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Reserved */ +#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ +#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ #define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ #define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ #define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/ @@ -316,7 +316,7 @@ * 28 4 extern edge * 29 3 software Reserved Reserved * 30 4 extern edge Reserved Reserved - * 31 5 extern level Reserved Reserved + * 31 5 extern level DPORT ACCESS DPORT ACCESS ************************************************************************************************************* */ @@ -328,6 +328,7 @@ #define ETS_FRC1_INUM 22 #define ETS_T1_WDT_INUM 24 #define ETS_CACHEERR_INUM 25 +#define ETS_DPORT_INUM 31 //CPU0 Interrupt number used in ROM, should be cancelled in SDK #define ETS_SLC_INUM 1 diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 676b9f33ce..cf8711d298 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -30,6 +30,8 @@ #include "soc_log.h" #include "sdkconfig.h" +#include "esp_dport_access.h" + #define MHZ (1000000) /* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */ @@ -332,7 +334,7 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) uint32_t delay_xtal_switch = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ? DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_150K : DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_32K; ets_delay_us(delay_xtal_switch); - REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); + DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); @@ -361,13 +363,13 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); rtc_clk_bbpll_set(xtal_freq, cpu_freq); if (cpu_freq == RTC_CPU_FREQ_80M) { - REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); + DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); ets_update_cpu_frequency(80); } else if (cpu_freq == RTC_CPU_FREQ_160M) { - REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1); + DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1); ets_update_cpu_frequency(160); } else if (cpu_freq == RTC_CPU_FREQ_240M) { - REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2); + DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2); ets_update_cpu_frequency(240); } REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL); @@ -392,7 +394,7 @@ rtc_cpu_freq_t rtc_clk_cpu_freq_get() break; } case RTC_CNTL_SOC_CLK_SEL_PLL: { - uint32_t cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); + uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); if (cpuperiod_sel == 0) { return RTC_CPU_FREQ_80M; } else if (cpuperiod_sel == 1) { diff --git a/components/soc/esp32/rtc_init.c b/components/soc/esp32/rtc_init.c index ca0c3a9c7e..a7cec5f34d 100644 --- a/components/soc/esp32/rtc_init.c +++ b/components/soc/esp32/rtc_init.c @@ -19,6 +19,7 @@ #include "soc/rtc_cntl_reg.h" #include "soc/dport_reg.h" +#include "esp_dport_access.h" void rtc_init(rtc_config_t cfg) { @@ -38,18 +39,18 @@ void rtc_init(rtc_config_t cfg) if (cfg.clkctl_init) { //clear CMMU clock force on - CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_FORCE_ON); - CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_FORCE_ON); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_FORCE_ON); + DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_FORCE_ON); //clear rom clock force on - SET_PERI_REG_BITS(DPORT_ROM_FO_CTRL_REG, DPORT_SHARE_ROM_FO, 0, DPORT_SHARE_ROM_FO_S); - CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_APP_ROM_FO); - CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_PRO_ROM_FO); + DPORT_SET_PERI_REG_BITS(DPORT_ROM_FO_CTRL_REG, DPORT_SHARE_ROM_FO, 0, DPORT_SHARE_ROM_FO_S); + DPORT_CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_APP_ROM_FO); + DPORT_CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_PRO_ROM_FO); //clear sram clock force on - SET_PERI_REG_BITS(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_0, 0, DPORT_SRAM_FO_0_S); - CLEAR_PERI_REG_MASK(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_1); + DPORT_SET_PERI_REG_BITS(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_0, 0, DPORT_SRAM_FO_0_S); + DPORT_CLEAR_PERI_REG_MASK(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_1); //clear tag clock force on - CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_APP_CACHE_TAG_FORCE_ON); - CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_PRO_CACHE_TAG_FORCE_ON); + DPORT_CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_APP_CACHE_TAG_FORCE_ON); + DPORT_CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_PRO_CACHE_TAG_FORCE_ON); } if (cfg.pwrctl_init) { diff --git a/components/soc/esp32/rtc_sleep.c b/components/soc/esp32/rtc_sleep.c index 5917d595de..d78beb1edf 100644 --- a/components/soc/esp32/rtc_sleep.c +++ b/components/soc/esp32/rtc_sleep.c @@ -25,6 +25,7 @@ #include "soc/fe_reg.h" #include "soc/rtc.h" #include "rom/ets_sys.h" +#include "esp_dport_access.h" #define MHZ (1000000) @@ -75,7 +76,7 @@ static void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, ~cfg.dig_pd); REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, ~cfg.rtc_pd); REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, ~cfg.rtc_pd); - REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd); + DPORT_REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd); REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, ~cfg.i2s_pd); REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, ~cfg.i2s_pd); REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, ~cfg.bb_pd); diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index b4e5fa6db5..159b18ad6f 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -29,6 +29,7 @@ #include "esp_attr.h" #include "esp_intr_alloc.h" #include "esp_spi_flash.h" +#include "esp_dport_access.h" #include "esp_log.h" @@ -251,17 +252,17 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_st { uint32_t ret = 0; if (cpuid == 0) { - ret |= GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0); - while (GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) { + ret |= DPORT_GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0); + while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) { ; } - SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S); + DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S); } else { - ret |= GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0); - while (GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) { + ret |= DPORT_GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0); + while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) { ; } - SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S); + DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S); } *saved_state = ret; } @@ -269,17 +270,17 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_st static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state) { if (cpuid == 0) { - SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S); - SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0); + DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S); + DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0); } else { - SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S); - SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0); + DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S); + DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0); } } IRAM_ATTR bool spi_flash_cache_enabled() { - return REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) - && REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE); + return DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) + && DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE); } diff --git a/components/xtensa-debug-module/trax.c b/components/xtensa-debug-module/trax.c index 15a125584e..0da109f564 100644 --- a/components/xtensa-debug-module/trax.c +++ b/components/xtensa-debug-module/trax.c @@ -16,6 +16,7 @@ #include "soc/dport_reg.h" #include "sdkconfig.h" #include "esp_err.h" +#include "esp_dport_access.h" #include "eri.h" #include "xtensa-debug-module.h" #include "trax.h" @@ -38,12 +39,12 @@ int trax_enable(trax_ena_select_t which) if (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP) return ESP_ERR_NO_MEM; #endif if (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP) { - WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, (which == TRAX_ENA_PRO_APP_SWAP)?TRACEMEM_MUX_PROBLK1_APPBLK0:TRACEMEM_MUX_PROBLK0_APPBLK1); + DPORT_WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, (which == TRAX_ENA_PRO_APP_SWAP)?TRACEMEM_MUX_PROBLK1_APPBLK0:TRACEMEM_MUX_PROBLK0_APPBLK1); } else { - WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK0_ONLY); + DPORT_WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK0_ONLY); } - WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP || which == TRAX_ENA_PRO)); - WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP || which == TRAX_ENA_APP)); + DPORT_WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP || which == TRAX_ENA_PRO)); + DPORT_WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP || which == TRAX_ENA_APP)); return ESP_OK; }