From f7e2e456e41145f6922b5c6a53ee3f003a389aa7 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Wed, 18 Jan 2017 18:31:06 +0800 Subject: [PATCH] intr_alloc: mark inline asm operand as earlyclobber When compiling in release mode, compiler was choosing same register for oldint and intmask variables, so INTENABLE was never modified. This effectively broke disabling of non-IRAM interrupts during flash operations, observed in the existing tests if task watchdog is enabled. This change adds an extra constraint tells the compiler that output operand should not be placed into the same register as an input one. --- components/esp32/intr_alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp32/intr_alloc.c b/components/esp32/intr_alloc.c index bfd6c51206..d9cc627e17 100644 --- a/components/esp32/intr_alloc.c +++ b/components/esp32/intr_alloc.c @@ -700,7 +700,7 @@ void esp_intr_noniram_disable() "and a3,%0,%1\n" //mask ints that need disabling "wsr a3,INTENABLE\n" //write back "rsync\n" - :"=r"(oldint):"r"(intmask):"a3"); + :"=&r"(oldint):"r"(intmask):"a3"); //Save which ints we did disable non_iram_int_disabled[cpu]=oldint&non_iram_int_mask[cpu]; }