From f67044c82264b38efe0a66d6bc21d18c49c868c7 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Tue, 12 May 2020 02:31:30 +0800 Subject: [PATCH] spi: simplify the caps header The mapping logic from register address to instance number is moved into the LL --- .../soc/soc/esp32/include/soc/spi_caps.h | 4 ++-- .../soc/soc/esp32s2/include/soc/spi_caps.h | 17 ++++---------- .../soc/src/esp32/include/hal/spi_flash_ll.h | 23 +++++++++++++------ .../src/esp32s2/include/hal/gpspi_flash_ll.h | 19 +++++++++------ .../src/esp32s2/include/hal/spi_flash_ll.h | 6 +++++ .../src/esp32s2/include/hal/spimem_flash_ll.h | 9 ++++---- .../soc/src/hal/spi_flash_hal_common.inc | 5 ++-- 7 files changed, 48 insertions(+), 35 deletions(-) diff --git a/components/soc/soc/esp32/include/soc/spi_caps.h b/components/soc/soc/esp32/include/soc/spi_caps.h index 722ae57352..fe7461a452 100644 --- a/components/soc/soc/esp32/include/soc/spi_caps.h +++ b/components/soc/soc/esp32/include/soc/spi_caps.h @@ -60,8 +60,8 @@ //#define SOC_SPI_SUPPORT_CD_SIG // Peripheral supports DIO, DOUT, QIO, or QOUT -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) 1 +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;}) // Peripheral doesn't support output given level during its "dummy phase" -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) 0 +#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_host) ({(void)spi_host; 0;}) diff --git a/components/soc/soc/esp32s2/include/soc/spi_caps.h b/components/soc/soc/esp32s2/include/soc/spi_caps.h index e09e6e4dc4..a34e55fdd7 100644 --- a/components/soc/soc/esp32s2/include/soc/spi_caps.h +++ b/components/soc/soc/esp32s2/include/soc/spi_caps.h @@ -47,20 +47,11 @@ #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 -#ifdef __cplusplus -extern "C" { -#endif -struct spi_dev_s; -extern volatile struct spi_dev_s GPSPI3; -struct spi_mem_dev_s; -extern volatile struct spi_mem_dev_s SPIMEM1; -#ifdef __cplusplus -} -#endif - // Peripheral supports DIO, DOUT, QIO, or QOUT -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3)) +// VSPI (SPI3) only support 1-bit mode +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2) // Peripheral supports output given level during its "dummy phase" -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) ((void*)spi_dev == (void*)&SPIMEM1) +// Only SPI1 supports this feature +#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id) ((host_id) == 0) diff --git a/components/soc/src/esp32/include/hal/spi_flash_ll.h b/components/soc/src/esp32/include/hal/spi_flash_ll.h index d47396f545..74f37db4be 100644 --- a/components/soc/src/esp32/include/hal/spi_flash_ll.h +++ b/components/soc/src/esp32/include/hal/spi_flash_ll.h @@ -43,7 +43,16 @@ extern "C" { #define SPI_FLASH_LL_CLKREG_VAL_80MHZ ((spi_flash_ll_clock_reg_t){.val=0x80000000}) ///< Clock set to 80 MHz /// Get the start address of SPI peripheral registers by the host ID -#define spi_flash_ll_get_hw(host_id) ((host_id)==SPI1_HOST? &SPI1:((host_id)==SPI2_HOST?&SPI2:((host_id)==SPI3_HOST?&SPI3:({abort();(spi_dev_t*)0;})))) +#define spi_flash_ll_get_hw(host_id) ( ((host_id)==SPI1_HOST) ? &SPI1 :(\ + ((host_id)==SPI2_HOST) ? &SPI2 :(\ + ((host_id)==SPI3_HOST) ? &SPI3 :(\ + {abort();(spi_dev_t*)0;}\ + ))) ) +#define spi_flash_ll_hw_get_id(dev) ( ((dev) == &SPI1) ? SPI1_HOST :(\ + ((dev) == &SPI2) ? SPI2_HOST :(\ + ((dev) == &SPI3) ? SPI3_HOST :(\ + -1\ + ))) ) /// Empty function to be compatible with new version chips. #define spi_flash_ll_set_dummy_out(dev, out_en, out_lev) @@ -161,12 +170,12 @@ static inline void spi_flash_ll_write_word(spi_dev_t *dev, uint32_t word) /** * Set the data to be written in the data buffer. - * + * * @param dev Beginning address of the peripheral registers. - * @param buffer Buffer holding the data + * @param buffer Buffer holding the data * @param length Length of data in bytes. */ -static inline void spi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length) +static inline void spi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length) { // Load data registers, word at a time int num_words = (length + 3) >> 2; @@ -324,10 +333,10 @@ static inline void spi_flash_ll_set_command8(spi_dev_t *dev, uint8_t command) /** * Get the address length that is set in register, in bits. - * + * * @param dev Beginning address of the peripheral registers. - * - */ + * + */ static inline int spi_flash_ll_get_addr_bitlen(spi_dev_t *dev) { return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; diff --git a/components/soc/src/esp32s2/include/hal/gpspi_flash_ll.h b/components/soc/src/esp32s2/include/hal/gpspi_flash_ll.h index 993370dc4d..b53b8eabdb 100644 --- a/components/soc/src/esp32s2/include/hal/gpspi_flash_ll.h +++ b/components/soc/src/esp32s2/include/hal/gpspi_flash_ll.h @@ -34,9 +34,14 @@ extern "C" { #endif -#define gpspi_flash_ll_get_hw(host_id) (((host_id)==SPI2_HOST ? &GPSPI2 \ - : ((host_id)==SPI3_HOST ? &GPSPI3 \ - : ({abort();(spi_dev_t*)0;})))) +#define gpspi_flash_ll_get_hw(host_id) ( ((host_id)==SPI2_HOST) ? &GPSPI2 : (\ + ((host_id)==SPI3_HOST) ? &GPSPI3 : (\ + {abort();(spi_dev_t*)0;}\ + )) ) +#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : (\ + ((dev) == (void*)&GPSPI3) ? SPI3_HOST : (\ + -1 \ + )) ) typedef typeof(GPSPI2.clock) gpspi_flash_ll_clock_reg_t; @@ -286,10 +291,10 @@ static inline void gpspi_flash_ll_set_command8(spi_dev_t *dev, uint8_t command) /** * Get the address length that is set in register, in bits. - * + * * @param dev Beginning address of the peripheral registers. - * - */ + * + */ static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev) { return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; @@ -346,7 +351,7 @@ static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) * * @param dev Beginning address of the peripheral registers. * @param out_en whether to enable IO output for dummy phase - * @param out_level dummy output level + * @param out_level dummy output level */ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev) { diff --git a/components/soc/src/esp32s2/include/hal/spi_flash_ll.h b/components/soc/src/esp32s2/include/hal/spi_flash_ll.h index 383c8275a3..d31bf2a50f 100644 --- a/components/soc/src/esp32s2/include/hal/spi_flash_ll.h +++ b/components/soc/src/esp32s2/include/hal/spi_flash_ll.h @@ -41,6 +41,12 @@ extern "C" { #define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \ : gpspi_flash_ll_get_hw(host_id))) +#define spi_flash_ll_hw_get_id(dev) ({int dev_id = spimem_flash_ll_hw_get_id(dev); \ + if (dev_id < 0) {\ + dev_id = gpspi_flash_ll_hw_get_id(dev);\ + }\ + dev_id; \ + }) typedef union { gpspi_flash_ll_clock_reg_t gpspi; diff --git a/components/soc/src/esp32s2/include/hal/spimem_flash_ll.h b/components/soc/src/esp32s2/include/hal/spimem_flash_ll.h index dc8b396114..cb257d7f3f 100644 --- a/components/soc/src/esp32s2/include/hal/spimem_flash_ll.h +++ b/components/soc/src/esp32s2/include/hal/spimem_flash_ll.h @@ -35,7 +35,8 @@ extern "C" { #endif -#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL )) +#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL )) +#define spimem_flash_ll_hw_get_id(dev) ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1) typedef typeof(SPIMEM1.clock) spimem_flash_ll_clock_reg_t; @@ -324,10 +325,10 @@ static inline void spimem_flash_ll_set_command8(spi_mem_dev_t *dev, uint8_t comm /** * Get the address length that is set in register, in bits. - * + * * @param dev Beginning address of the peripheral registers. - * - */ + * + */ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev) { return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; diff --git a/components/soc/src/hal/spi_flash_hal_common.inc b/components/soc/src/hal/spi_flash_hal_common.inc index f42a1f6ba2..b84c6181d7 100644 --- a/components/soc/src/hal/spi_flash_hal_common.inc +++ b/components/soc/src/hal/spi_flash_hal_common.inc @@ -51,11 +51,12 @@ esp_err_t spi_flash_hal_configure_host_io_mode( esp_flash_io_mode_t io_mode) { spi_dev_t *dev = get_spi_dev(host); + int host_id = spi_flash_ll_hw_get_id(dev); - if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(dev) && io_mode > SPI_FLASH_FASTRD) { + if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) && io_mode > SPI_FLASH_FASTRD) { return ESP_ERR_NOT_SUPPORTED; } - if (addr_bitlen > 24 && SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(dev)) { + if (addr_bitlen > 24 && SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id)) { /* * The extra address bits (24-addr_bitlen) are used to control the M7-M0 bits right after * the address field, to avoid the flash going into continuous read mode.