From f790fe0e1f71ccb2e6315e32f290266a09a58571 Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Thu, 9 Feb 2023 17:11:37 +0530 Subject: [PATCH 1/3] clk_gate_ll: fix issue with DS peripheral clk reset In ESP32-H2, every peripheral reset enable bit is in different register (unlike some of the previous SoCs) and hence they must be handled with multiple register write operations. This allows AES, MPI peripherals to works correctly after DS peripheral has done some operations. --- .../hal/esp32h2/include/hal/clk_gate_ll.h | 37 ++++++++----------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h index 349bc4aa74..7d5b6001db 100644 --- a/components/hal/esp32h2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h @@ -129,29 +129,24 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en case PERIPH_ETM_MODULE: return PCR_ETM_RST_EN; case PERIPH_AES_MODULE: - if (enable == true) { - // Clear reset on digital signature, otherwise AES unit is held in reset also. - return (PCR_AES_RST_EN | PCR_DS_RST_EN); - } else { - //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively. - return PCR_AES_RST_EN; - } + if (enable == true) { + // Clear reset on digital signature, otherwise AES unit is held in reset + DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + } + return PCR_AES_RST_EN; case PERIPH_SHA_MODULE: - if (enable == true) { - // Clear reset on digital signature and HMAC, otherwise SHA is held in reset - return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN); - } else { - // Don't assert reset on secure boot, otherwise AES is held in reset - return PCR_SHA_RST_EN; - } + if (enable == true) { + // Clear reset on digital signature and HMAC, otherwise SHA is held in reset + DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + DPORT_CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); + } + return PCR_SHA_RST_EN; case PERIPH_RSA_MODULE: - if (enable == true) { - /* also clear reset on digital signature, otherwise RSA is held in reset */ - return (PCR_RSA_RST_EN | PCR_DS_RST_EN); - } else { - /* don't reset digital signature unit, as this resets AES also */ - return PCR_RSA_RST_EN; - } + if (enable == true) { + // Clear reset on digital signature, otherwise RSA is held in reset + DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + } + return PCR_RSA_RST_EN; case PERIPH_HMAC_MODULE: return PCR_HMAC_RST_EN; case PERIPH_DS_MODULE: From 06def61fe8852863a26578770006ea16bdac7738 Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Thu, 9 Feb 2023 17:15:22 +0530 Subject: [PATCH 2/3] clk_gate_ll: fix issue with DS peripheral clk reset In ESP32-C6, every peripheral reset enable bit is in different register (unlike some of the previous SoCs) and hence they must be handled with multiple register write operations. This allows AES, MPI peripherals to works correctly after DS peripheral has done some operations. --- .../hal/esp32c6/include/hal/clk_gate_ll.h | 37 ++++++++----------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h index 2e683d5d7f..bb4f50c4b8 100644 --- a/components/hal/esp32c6/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h @@ -139,29 +139,24 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en case PERIPH_TEMPSENSOR_MODULE: return PCR_TSENS_RST_EN; case PERIPH_AES_MODULE: - if (enable == true) { - // Clear reset on digital signature, otherwise AES unit is held in reset also. - return (PCR_AES_RST_EN | PCR_DS_RST_EN); - } else { - //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively. - return PCR_AES_RST_EN; - } + if (enable == true) { + // Clear reset on digital signature, otherwise AES unit is held in reset + DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + } + return PCR_AES_RST_EN; case PERIPH_SHA_MODULE: - if (enable == true) { - // Clear reset on digital signature and HMAC, otherwise SHA is held in reset - return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN); - } else { - // Don't assert reset on secure boot, otherwise AES is held in reset - return PCR_SHA_RST_EN; - } + if (enable == true) { + // Clear reset on digital signature and HMAC, otherwise SHA is held in reset + DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + DPORT_CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); + } + return PCR_SHA_RST_EN; case PERIPH_RSA_MODULE: - if (enable == true) { - /* also clear reset on digital signature, otherwise RSA is held in reset */ - return (PCR_RSA_RST_EN | PCR_DS_RST_EN); - } else { - /* don't reset digital signature unit, as this resets AES also */ - return PCR_RSA_RST_EN; - } + if (enable == true) { + // Clear reset on digital signature, otherwise RSA is held in reset + DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + } + return PCR_RSA_RST_EN; case PERIPH_HMAC_MODULE: return PCR_HMAC_RST_EN; case PERIPH_DS_MODULE: From 725e1fb3cc24bde573a4ec1b26ffa666eb07f6d1 Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Fri, 10 Feb 2023 10:48:45 +0530 Subject: [PATCH 3/3] clk_gate_ll: remove DPORT_ prefix as this is not required for H2/C6 --- .../hal/esp32c6/include/hal/clk_gate_ll.h | 26 +++++++++---------- .../hal/esp32h2/include/hal/clk_gate_ll.h | 26 +++++++++---------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h index bb4f50c4b8..df4004c48c 100644 --- a/components/hal/esp32c6/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h @@ -10,7 +10,7 @@ #include #include "soc/periph_defs.h" #include "soc/pcr_reg.h" -#include "soc/dport_access.h" +#include "soc/soc.h" #include "esp_attr.h" #ifdef __cplusplus @@ -141,20 +141,20 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en case PERIPH_AES_MODULE: if (enable == true) { // Clear reset on digital signature, otherwise AES unit is held in reset - DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); } return PCR_AES_RST_EN; case PERIPH_SHA_MODULE: if (enable == true) { // Clear reset on digital signature and HMAC, otherwise SHA is held in reset - DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); - DPORT_CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); + CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); } return PCR_SHA_RST_EN; case PERIPH_RSA_MODULE: if (enable == true) { // Clear reset on digital signature, otherwise RSA is held in reset - DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); } return PCR_RSA_RST_EN; case PERIPH_HMAC_MODULE: @@ -314,26 +314,26 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph) { - DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true)); + SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true)); } static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) { - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); - DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } static inline void periph_ll_reset(periph_module_t periph) { - DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) { - return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && - DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; + return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && + REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; } #ifdef __cplusplus diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h index 7d5b6001db..a5485aae47 100644 --- a/components/hal/esp32h2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h @@ -10,7 +10,7 @@ #include #include "soc/periph_defs.h" #include "soc/pcr_reg.h" -#include "soc/dport_access.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { @@ -131,20 +131,20 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en case PERIPH_AES_MODULE: if (enable == true) { // Clear reset on digital signature, otherwise AES unit is held in reset - DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); } return PCR_AES_RST_EN; case PERIPH_SHA_MODULE: if (enable == true) { // Clear reset on digital signature and HMAC, otherwise SHA is held in reset - DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); - DPORT_CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); + CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); } return PCR_SHA_RST_EN; case PERIPH_RSA_MODULE: if (enable == true) { // Clear reset on digital signature, otherwise RSA is held in reset - DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); } return PCR_RSA_RST_EN; case PERIPH_HMAC_MODULE: @@ -291,14 +291,14 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph) { - DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true)); + SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true)); } static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) { - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); - DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } static inline void periph_ll_wifi_bt_module_enable_clk_clear_rst(void) @@ -315,14 +315,14 @@ static inline void periph_ll_wifi_bt_module_disable_clk_set_rst(void) static inline void periph_ll_reset(periph_module_t periph) { - DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } static inline bool periph_ll_periph_enabled(periph_module_t periph) { - return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && - DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; + return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && + REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; } static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)