From f46e42bc1fc11fb6bc83a29d359793565f293e3a Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 23 Feb 2023 12:51:04 +0800 Subject: [PATCH] soc: update iram/dram addr range in ext_mem_defs.h --- components/soc/esp32c3/include/soc/cache_memory.h | 9 ++++----- components/soc/esp32s3/include/soc/cache_memory.h | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/components/soc/esp32c3/include/soc/cache_memory.h b/components/soc/esp32c3/include/soc/cache_memory.h index db558c4e50..350cc8dec9 100644 --- a/components/soc/esp32c3/include/soc/cache_memory.h +++ b/components/soc/esp32c3/include/soc/cache_memory.h @@ -19,18 +19,17 @@ extern "C" { #endif /*IRAM0 is connected with Cache IBUS0*/ -#define IRAM0_ADDRESS_LOW 0x40000000 -#define IRAM0_ADDRESS_HIGH 0x44000000 +#define IRAM0_ADDRESS_LOW 0x4037C000 +#define IRAM0_ADDRESS_HIGH 0x403E0000 #define IRAM0_CACHE_ADDRESS_LOW 0x42000000 #define IRAM0_CACHE_ADDRESS_HIGH 0x42800000 /*DRAM0 is connected with Cache DBUS0*/ -#define DRAM0_ADDRESS_LOW 0x3C000000 -#define DRAM0_ADDRESS_HIGH 0x40000000 +#define DRAM0_ADDRESS_LOW 0x3FC80000 +#define DRAM0_ADDRESS_HIGH 0x3FCE0000 #define DRAM0_CACHE_ADDRESS_LOW 0x3C000000 #define DRAM0_CACHE_ADDRESS_HIGH 0x3C800000 #define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH -#define ESP_CACHE_TEMP_ADDR 0x3C000000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) diff --git a/components/soc/esp32s3/include/soc/cache_memory.h b/components/soc/esp32s3/include/soc/cache_memory.h index 2d6f337c81..221a77b503 100644 --- a/components/soc/esp32s3/include/soc/cache_memory.h +++ b/components/soc/esp32s3/include/soc/cache_memory.h @@ -18,18 +18,17 @@ extern "C" { #endif /*IRAM0 is connected with Cache IBUS0*/ -#define IRAM0_ADDRESS_LOW 0x40000000 -#define IRAM0_ADDRESS_HIGH 0x44000000 +#define IRAM0_ADDRESS_LOW 0x40370000 +#define IRAM0_ADDRESS_HIGH 0x403E0000 #define IRAM0_CACHE_ADDRESS_LOW 0x42000000 #define IRAM0_CACHE_ADDRESS_HIGH 0x44000000 /*DRAM0 is connected with Cache DBUS0*/ -#define DRAM0_ADDRESS_LOW 0x3C000000 -#define DRAM0_ADDRESS_HIGH 0x40000000 +#define DRAM0_ADDRESS_LOW 0x3FC88000 +#define DRAM0_ADDRESS_HIGH 0x3FD00000 #define DRAM0_CACHE_ADDRESS_LOW 0x3C000000 #define DRAM0_CACHE_ADDRESS_HIGH 0x3E000000 #define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH -#define ESP_CACHE_TEMP_ADDR 0x3C800000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)