kopia lustrzana https://github.com/espressif/esp-idf
modify character conversion error and typo
Wangjialin
Wu Jian Gang
rodzic
c13ab62e4c
commit
f32823ff6c
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@ -525,15 +525,15 @@
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#define SARADC_XPD_HALL_FORCE_V 0x1
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#define SARADC_XPD_HALL_FORCE_S 26
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/* SARADC_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
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/*description: 1: wakeup interrupt is generated if SET1 is <EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD> 0:
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wakeup interrupt is generated only if SET1 & SET2 is both <EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD>*/
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/*description: 1: wakeup interrupt is generated if SET1 is "touched" 0:
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wakeup interrupt is generated only if SET1 & SET2 is both "touched"*/
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#define SARADC_TOUCH_OUT_1EN (BIT(25))
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#define SARADC_TOUCH_OUT_1EN_M (BIT(25))
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#define SARADC_TOUCH_OUT_1EN_V 0x1
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#define SARADC_TOUCH_OUT_1EN_S 25
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/* SARADC_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */
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/*description: 1: when the counter is greater then the threshold the touch
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pad is considered as <EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD> 0: when the counter is less than the threshold the touch pad is considered as <EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD>*/
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pad is considered as "touched" 0: when the counter is less than the threshold the touch pad is considered as "touched"*/
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#define SARADC_TOUCH_OUT_SEL (BIT(24))
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#define SARADC_TOUCH_OUT_SEL_M (BIT(24))
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#define SARADC_TOUCH_OUT_SEL_V 0x1
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@ -730,7 +730,7 @@
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#define SARADC_TOUCH_MEAS_DONE_V 0x1
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#define SARADC_TOUCH_MEAS_DONE_S 10
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/* SARADC_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */
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/*description: 10-bit register to indicate which pads are <EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD>*/
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/*description: 10-bit register to indicate which pads are "touched"*/
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#define SARADC_TOUCH_MEAS_EN 0x000003FF
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#define SARADC_TOUCH_MEAS_EN_M ((SARADC_TOUCH_MEAS_EN_V)<<(SARADC_TOUCH_MEAS_EN_S))
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#define SARADC_TOUCH_MEAS_EN_V 0x3FF
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@ -739,14 +739,14 @@
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#define SARADC_SAR_TOUCH_ENABLE_REG (DR_REG_SARADC_BASE + 0x008c)
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/* SARADC_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */
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/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is
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<EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD> only if at least one of touch pad in SET1 is <EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD>.*/
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"touched" only if at least one of touch pad in SET1 is "touched".*/
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#define SARADC_TOUCH_PAD_OUTEN1 0x000003FF
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#define SARADC_TOUCH_PAD_OUTEN1_M ((SARADC_TOUCH_PAD_OUTEN1_V)<<(SARADC_TOUCH_PAD_OUTEN1_S))
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#define SARADC_TOUCH_PAD_OUTEN1_V 0x3FF
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#define SARADC_TOUCH_PAD_OUTEN1_S 20
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/* SARADC_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */
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/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is
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<EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD> only if at least one of touch pad in SET2 is <EFBFBD><EFBFBD>touched<EFBFBD><EFBFBD>.*/
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"touched" only if at least one of touch pad in SET2 is "touched".*/
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#define SARADC_TOUCH_PAD_OUTEN2 0x000003FF
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#define SARADC_TOUCH_PAD_OUTEN2_M ((SARADC_TOUCH_PAD_OUTEN2_V)<<(SARADC_TOUCH_PAD_OUTEN2_S))
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#define SARADC_TOUCH_PAD_OUTEN2_V 0x3FF
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@ -187,7 +187,7 @@
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#define SPI_FREAD_QUAD_V 0x1
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#define SPI_FREAD_QUAD_S 20
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/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
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/*description: The Device ID is read out to SPI_RD_STATUS register£¬ this bit
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/*description: The Device ID is read out to SPI_RD_STATUS register, this bit
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combine with spi_flash_res bit. 1: enable 0: disable.*/
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#define SPI_RESANDRES (BIT(15))
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#define SPI_RESANDRES_M (BIT(15))
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@ -243,19 +243,19 @@
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#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10)
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/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */
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/*description: In the slave mode£¬it is the status for master to read out.*/
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/*description: In the slave mode,it is the status for master to read out.*/
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#define SPI_STATUS_EXT 0x000000FF
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#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S))
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#define SPI_STATUS_EXT_V 0xFF
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#define SPI_STATUS_EXT_S 24
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/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
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/*description: Mode bits in the flash fast read mode£¬ it is combined with spi_fastrd_mode bit.*/
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/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
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#define SPI_WB_MODE 0x000000FF
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#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S))
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#define SPI_WB_MODE_V 0xFF
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#define SPI_WB_MODE_S 16
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/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
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/*description: In the slave mode£¬ it is the status for master to read out.*/
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/*description: In the slave mode, it is the status for master to read out.*/
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#define SPI_STATUS 0x0000FFFF
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#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S))
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#define SPI_STATUS_V 0xFFFF
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@ -302,27 +302,27 @@
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#define SPI_MISO_DELAY_MODE_V 0x3
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#define SPI_MISO_DELAY_MODE_S 16
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/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */
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/*description: modify spi clock duty ratio when the value is lager than 8£¬
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/*description: modify spi clock duty ratio when the value is lager than 8,
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the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/
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#define SPI_CK_OUT_HIGH_MODE 0x0000000F
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#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S))
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#define SPI_CK_OUT_HIGH_MODE_V 0xF
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#define SPI_CK_OUT_HIGH_MODE_S 12
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/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
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/*description: modify spi clock duty ratio when the value is lager than 8£¬
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/*description: modify spi clock duty ratio when the value is lager than 8,
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the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/
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#define SPI_CK_OUT_LOW_MODE 0x0000000F
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#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S))
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#define SPI_CK_OUT_LOW_MODE_V 0xF
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#define SPI_CK_OUT_LOW_MODE_S 8
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/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */
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/*description: delay cycles of cs pin by spi clock£¬ this bits combined with spi_cs_hold bit.*/
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/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/
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#define SPI_HOLD_TIME 0x0000000F
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#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S))
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#define SPI_HOLD_TIME_V 0xF
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#define SPI_HOLD_TIME_S 4
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/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */
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/*description: (cycles-1) of ¡°prepare¡± phase by spi clock£¬ this bits combined
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/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined
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with spi_cs_setup bit.*/
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#define SPI_SETUP_TIME 0x0000000F
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#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S))
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@ -622,19 +622,19 @@
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#define SPI_CK_DIS_V 0x1
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#define SPI_CK_DIS_S 5
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/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
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/*description: SPI CS2 pin enable£¬ 1: disable CS2£¬ 0: spi_cs2 signal is from/to CS2 pin*/
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/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
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#define SPI_CS2_DIS (BIT(2))
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#define SPI_CS2_DIS_M (BIT(2))
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#define SPI_CS2_DIS_V 0x1
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#define SPI_CS2_DIS_S 2
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/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
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/*description: SPI CS1 pin enable£¬ 1: disable CS1£¬ 0: spi_cs1 signal is from/to CS1 pin*/
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/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/
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#define SPI_CS1_DIS (BIT(1))
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#define SPI_CS1_DIS_M (BIT(1))
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#define SPI_CS1_DIS_V 0x1
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#define SPI_CS1_DIS_S 1
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/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: SPI CS0 pin enable£¬ 1: disable CS0£¬ 0: spi_cs0 signal is from/to CS0 pin*/
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/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/
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#define SPI_CS0_DIS (BIT(0))
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#define SPI_CS0_DIS_M (BIT(0))
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#define SPI_CS0_DIS_V 0x1
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@ -642,7 +642,7 @@
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#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38)
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/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
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/*description: Software reset enable£¬ reset the spi clock line cs line and data lines.*/
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/*description: Software reset enable, reset the spi clock line cs line and data lines.*/
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#define SPI_SYNC_RESET (BIT(31))
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#define SPI_SYNC_RESET_M (BIT(31))
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#define SPI_SYNC_RESET_V 0x1
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@ -90,7 +90,7 @@
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#define UART_SW_XOFF_INT_RAW_V 0x1
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#define UART_SW_XOFF_INT_RAW_S 10
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/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
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/*description: This interrupt raw bit turns to high level when receiver recevies
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/*description: This interrupt raw bit turns to high level when receiver receives
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xoff char with uart_sw_flow_con_en is set to 1.*/
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#define UART_SW_XON_INT_RAW (BIT(9))
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#define UART_SW_XON_INT_RAW_M (BIT(9))
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@ -617,20 +617,20 @@
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#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)
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/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */
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/*description: This register is used to select the clock.1<EFBFBD><EFBFBD>apb clock<63><6B>ref_tick*/
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/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/
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#define UART_TICK_REF_ALWAYS_ON (BIT(27))
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#define UART_TICK_REF_ALWAYS_ON_M (BIT(27))
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#define UART_TICK_REF_ALWAYS_ON_V 0x1
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#define UART_TICK_REF_ALWAYS_ON_S 27
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/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
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/*description: 1<EFBFBD><EFBFBD>receiver stops storing data int fifo when data is wrong.
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0<EFBFBD><EFBFBD>receiver stores the data even if the received data is wrong.*/
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/*description: 1.receiver stops storing data int fifo when data is wrong.
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0.receiver stores the data even if the received data is wrong.*/
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#define UART_ERR_WR_MASK (BIT(26))
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#define UART_ERR_WR_MASK_M (BIT(26))
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#define UART_ERR_WR_MASK_V 0x1
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#define UART_ERR_WR_MASK_S 26
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/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
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/*description: 1<EFBFBD><EFBFBD>force clock on for registers<72><73>support clock only when write registers*/
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/*description: 1.force clock on for registers.support clock only when write registers*/
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#define UART_CLK_EN (BIT(25))
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#define UART_CLK_EN_M (BIT(25))
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#define UART_CLK_EN_V 0x1
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@ -714,8 +714,8 @@
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#define UART_IRDA_TX_INV_V 0x1
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#define UART_IRDA_TX_INV_S 12
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/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
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/*description: 1<EFBFBD><EFBFBD>the irda transmitter's 11th bit is the same to the 10th bit.
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0<EFBFBD><EFBFBD>set irda transmitter's 11th bit to 0.*/
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/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit.
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0.set irda transmitter's 11th bit to 0.*/
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#define UART_IRDA_WCTL (BIT(11))
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#define UART_IRDA_WCTL_M (BIT(11))
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#define UART_IRDA_WCTL_V 0x1
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@ -800,7 +800,7 @@
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#define UART_RX_FLOW_EN_V 0x1
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#define UART_RX_FLOW_EN_S 23
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/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */
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/*description: when receiver receives more data than its threshold value<EFBFBD><EFBFBD>
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/*description: when receiver receives more data than its threshold value.
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receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/
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#define UART_RX_FLOW_THRHD 0x0000007F
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#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
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@ -808,13 +808,13 @@
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#define UART_RX_FLOW_THRHD_S 16
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/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */
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/*description: when the data amount in transmitter fifo is less than its threshold
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value<EFBFBD><EFBFBD> it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/
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value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/
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#define UART_TXFIFO_EMPTY_THRHD 0x0000007F
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#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
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#define UART_TXFIFO_EMPTY_THRHD_V 0x7F
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#define UART_TXFIFO_EMPTY_THRHD_S 8
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/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */
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/*description: When receiver receives more data than its threshold value<EFBFBD><EFBFBD>receiver
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/*description: When receiver receives more data than its threshold value.receiver
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will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/
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#define UART_RXFIFO_FULL_THRHD 0x0000007F
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#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
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@ -824,7 +824,7 @@
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#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)
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/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
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/*description: This register stores the value of the minimum duration time for
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the low level pulse<EFBFBD><EFBFBD> it is used in baudrate-detect process.*/
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the low level pulse. it is used in baudrate-detect process.*/
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#define UART_LOWPULSE_MIN_CNT 0x000FFFFF
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#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
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#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF
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@ -833,7 +833,7 @@
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#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)
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/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
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/*description: This register stores the value of the maxinum duration time
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for the high level pulse<EFBFBD><EFBFBD> it is used in baudrate-detect process.*/
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for the high level pulse. it is used in baudrate-detect process.*/
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#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF
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#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
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#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF
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@ -841,7 +841,7 @@
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#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
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/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
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/*description: This register stores the count of rxd edge change<EFBFBD><EFBFBD> it is used
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/*description: This register stores the count of rxd edge change. it is used
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in baudrate-detect process.*/
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#define UART_RXD_EDGE_CNT 0x000003FF
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#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
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@ -850,13 +850,13 @@
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#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)
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/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/*description: Set this bit to send xoff char<EFBFBD><EFBFBD> it is cleared by hardware automatically.*/
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/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/
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#define UART_SEND_XOFF (BIT(5))
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#define UART_SEND_XOFF_M (BIT(5))
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#define UART_SEND_XOFF_V 0x1
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#define UART_SEND_XOFF_S 5
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/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */
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/*description: Set this bit to send xon char<EFBFBD><EFBFBD> it is cleared by hardware automatically.*/
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/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/
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#define UART_SEND_XON (BIT(4))
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#define UART_SEND_XON_M (BIT(4))
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#define UART_SEND_XON_V 0x1
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@ -889,7 +889,7 @@
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#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
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/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
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/*description: When the input rxd edge changes more than this register value<EFBFBD><EFBFBD>
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/*description: When the input rxd edge changes more than this register value.
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the uart is active from light sleeping mode.*/
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#define UART_ACTIVE_THRESHOLD 0x000003FF
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#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
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@ -911,14 +911,14 @@
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#define UART_XON_CHAR_S 16
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/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */
|
||||
/*description: When the data amount in receiver's fifo is less than this register
|
||||
value<EFBFBD><EFBFBD> it will send a xon char with uart_sw_flow_con_en set to 1.*/
|
||||
value. it will send a xon char with uart_sw_flow_con_en set to 1.*/
|
||||
#define UART_XOFF_THRESHOLD 0x000000FF
|
||||
#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
|
||||
#define UART_XOFF_THRESHOLD_V 0xFF
|
||||
#define UART_XOFF_THRESHOLD_S 8
|
||||
/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: when the data amount in receiver's fifo is more than this register
|
||||
value<EFBFBD><EFBFBD> it will send a xoff char with uart_sw_flow_con_en set to 1.*/
|
||||
value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/
|
||||
#define UART_XON_THRESHOLD 0x000000FF
|
||||
#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
|
||||
#define UART_XON_THRESHOLD_V 0xFF
|
||||
|
|
@ -940,7 +940,7 @@
|
|||
#define UART_TX_IDLE_NUM_S 10
|
||||
/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
|
||||
/*description: when receiver takes more time than this register value to receive
|
||||
a byte data<EFBFBD><EFBFBD> it will produce frame end signal for uhci to stop receiving data.*/
|
||||
a byte data. it will produce frame end signal for uhci to stop receiving data.*/
|
||||
#define UART_RX_IDLE_THRHD 0x000003FF
|
||||
#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
|
||||
#define UART_RX_IDLE_THRHD_V 0x3FF
|
||||
|
|
@ -995,7 +995,7 @@
|
|||
#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48)
|
||||
/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
|
||||
/*description: This register is used to configure the idle duration time before
|
||||
the first at_cmd is received by receiver<EFBFBD><EFBFBD> when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
|
||||
the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
|
||||
#define UART_PRE_IDLE_NUM 0x00FFFFFF
|
||||
#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
|
||||
#define UART_PRE_IDLE_NUM_V 0xFFFFFF
|
||||
|
|
@ -1004,7 +1004,7 @@
|
|||
#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c)
|
||||
/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
|
||||
/*description: This register is used to configure the duration time between
|
||||
the last at_cmd and the next data<EFBFBD><EFBFBD> when the duration is less than this register value it will not take the previous data as at_cmd char.*/
|
||||
the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/
|
||||
#define UART_POST_IDLE_NUM 0x00FFFFFF
|
||||
#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
|
||||
#define UART_POST_IDLE_NUM_V 0xFFFFFF
|
||||
|
|
@ -1013,7 +1013,7 @@
|
|||
#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50)
|
||||
/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */
|
||||
/*description: This register is used to configure the duration time between
|
||||
the at_cmd chars<EFBFBD><EFBFBD> when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/
|
||||
the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/
|
||||
#define UART_RX_GAP_TOUT 0x00FFFFFF
|
||||
#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
|
||||
#define UART_RX_GAP_TOUT_V 0xFFFFFF
|
||||
|
|
@ -1086,7 +1086,7 @@
|
|||
#define UART_RX_SIZE_V 0xF
|
||||
#define UART_RX_SIZE_S 3
|
||||
/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to power down mem<EFBFBD><EFBFBD>when reg_mem_pd registers in
|
||||
/*description: Set this bit to power down mem.when reg_mem_pd registers in
|
||||
the 3 uarts are all set to 1 mem will enter low power mode.*/
|
||||
#define UART_MEM_PD (BIT(0))
|
||||
#define UART_MEM_PD_M (BIT(0))
|
||||
|
|
@ -1125,7 +1125,7 @@
|
|||
|
||||
#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68)
|
||||
/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
|
||||
/*description: This register stores the count of rxd posedge edge<EFBFBD><EFBFBD> it is used
|
||||
/*description: This register stores the count of rxd posedge edge. it is used
|
||||
in boudrate-detect process.*/
|
||||
#define UART_POSEDGE_MIN_CNT 0x000FFFFF
|
||||
#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
|
||||
|
|
@ -1134,7 +1134,7 @@
|
|||
|
||||
#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c)
|
||||
/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
|
||||
/*description: This register stores the count of rxd negedge edge<EFBFBD><EFBFBD> it is used
|
||||
/*description: This register stores the count of rxd negedge edge. it is used
|
||||
in boudrate-detect process.*/
|
||||
#define UART_NEGEDGE_MIN_CNT 0x000FFFFF
|
||||
#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
|
||||
|
|
|
|||
|
|
@ -859,7 +859,7 @@
|
|||
#define UHCI_AHB_TESTADDR_V 0x3
|
||||
#define UHCI_AHB_TESTADDR_S 4
|
||||
/* UHCI_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: bit2 is ahb bus test enable £¬bit1 is used to choose wrtie(1)
|
||||
/*description: bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1)
|
||||
or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
|
||||
#define UHCI_AHB_TESTMODE 0x00000007
|
||||
#define UHCI_AHB_TESTMODE_M ((UHCI_AHB_TESTMODE_V)<<(UHCI_AHB_TESTMODE_S))
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue