kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'esp32_s2_s3_cpu_freq_to_pll' into 'master'
EspS2/S3: fixed the bug of insufficient voltage when the CPU switches frequency See merge request espressif/esp-idf!25396pull/12330/head
commit
efb9d9e7d4
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -256,13 +256,39 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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*/
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static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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{
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int dbias = (cpu_freq_mhz == 240) ? DIG_DBIAS_240M : DIG_DBIAS_80M_160M;
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/* To avoid the problem of insufficient voltage when the CPU frequency is switched:
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* When the CPU frequency is switched from low to high, it is necessary to
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* increase the voltage first and then increase the frequency, and the frequency
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* needs to wait for the voltage to fully increase before proceeding.
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* When the frequency of the CPU is switched from high to low, it is necessary
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* to reduce the frequency first and then reduce the voltage.
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*/
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rtc_cpu_freq_config_t cur_config;
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rtc_clk_cpu_freq_get_config(&cur_config);
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/* cpu_frequency < 240M: dbias = DIG_DBIAS_XTAL_80M_160M;
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* cpu_frequency = 240M: dbias = DIG_DBIAS_240M;
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*/
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if (cpu_freq_mhz > cur_config.freq_mhz) {
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if (cpu_freq_mhz == 240) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_DBIAS_240M);
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esp_rom_delay_us(40);
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}
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}
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clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
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clk_ll_cpu_set_divider(1);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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rtc_clk_apb_freq_update(80 * MHZ);
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esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
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if (cpu_freq_mhz < cur_config.freq_mhz) {
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if (cur_config.freq_mhz == 240) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL_80M_160M);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_DBIAS_XTAL_80M_160M);
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esp_rom_delay_us(40);
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}
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}
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}
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bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config)
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@ -411,6 +437,9 @@ void rtc_clk_cpu_set_to_default_config(void)
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*/
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static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
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{
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rtc_cpu_freq_config_t cur_config;
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rtc_clk_cpu_freq_get_config(&cur_config);
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esp_rom_set_cpu_ticks_per_us(cpu_freq);
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/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
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clk_ll_cpu_set_divider(1);
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@ -419,15 +448,24 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
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rtc_clk_apb_freq_update(cpu_freq * MHZ);
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/* lower the voltage */
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int dbias = (cpu_freq <= 2) ? DIG_DBIAS_2M : DIG_DBIAS_XTAL;
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
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/* lower the voltage
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* cpu_frequency < 240M: dbias = DIG_DBIAS_XTAL_80M_160M;
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* cpu_frequency = 240M: dbias = DIG_DBIAS_240M;
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*/
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if (cur_config.freq_mhz == 240) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL_80M_160M);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_DBIAS_XTAL_80M_160M);
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esp_rom_delay_us(40);
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}
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}
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static void rtc_clk_cpu_freq_to_8m(void)
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{
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assert(0 && "LDO dbias need to modified");
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esp_rom_set_cpu_ticks_per_us(8);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
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esp_rom_delay_us(40);
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clk_ll_cpu_set_divider(1);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
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rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -185,17 +185,6 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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*/
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static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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{
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/* cpu_frequency < 240M: dbias = pvt-dig + 2;
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cpu_frequency = 240M: dbias = pvt-dig + 3;
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*/
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if (cpu_freq_mhz != 240) {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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} else {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_240m);
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}
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esp_rom_delay_us(40);
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/* There are totally 6 LDO slaves(all on by default). At the moment of swithing LDO slave, LDO voltage will also change instantaneously.
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* LDO slave can reduce the voltage change caused by switching frequency.
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@ -207,21 +196,31 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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int pd_slave = cpu_freq_mhz / 80;
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rtc_cpu_freq_config_t cur_config;
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rtc_clk_cpu_freq_get_config(&cur_config);
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/* cpu_frequency < 240M: dbias = pvt-dig + 2;
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* cpu_frequency = 240M: dbias = pvt-dig + 3;
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*/
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if (cpu_freq_mhz > cur_config.freq_mhz) {
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if (cpu_freq_mhz == 240) {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_240m);
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esp_rom_delay_us(40);
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}
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REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE >> pd_slave);
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clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
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clk_ll_cpu_set_divider(1);
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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rtc_clk_apb_freq_update(80 * MHZ);
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esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
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} else {
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clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
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clk_ll_cpu_set_divider(1);
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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rtc_clk_apb_freq_update(80 * MHZ);
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esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
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}
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clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
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clk_ll_cpu_set_divider(1);
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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rtc_clk_apb_freq_update(80 * MHZ);
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esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
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if (cpu_freq_mhz < cur_config.freq_mhz) {
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if (cur_config.freq_mhz == 240) {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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esp_rom_delay_us(40);
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}
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REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE >> pd_slave);
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}
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}
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@ -376,9 +375,9 @@ void rtc_clk_cpu_set_to_default_config(void)
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*/
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void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
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{
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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esp_rom_delay_us(40);
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rtc_cpu_freq_config_t cur_config;
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rtc_clk_cpu_freq_get_config(&cur_config);
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esp_rom_set_cpu_ticks_per_us(cpu_freq);
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/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
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clk_ll_cpu_set_divider(1);
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
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rtc_clk_apb_freq_update(cpu_freq * MHZ);
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if (cur_config.freq_mhz == 240) {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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esp_rom_delay_us(40);
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}
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REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE);
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}
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static void rtc_clk_cpu_freq_to_8m(void)
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{
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assert(0 && "LDO dbias need to modified");
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esp_rom_set_cpu_ticks_per_us(20);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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esp_rom_delay_us(40);
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clk_ll_cpu_set_divider(1);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
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rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE);
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -84,7 +84,10 @@ extern "C" {
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
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#endif
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#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25
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#define RTC_DBIAS_240M RTC_CNTL_DBIAS_1V25
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_XTAL_80M_160M RTC_CNTL_DBIAS_1V10
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#define RTC_DBIAS_XTAL_80M_160M RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
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#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
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