kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'refactor/add_peripheral_signal_description' into 'master'
timer_group: driver on ESP32-S3 Closes IDF-1774 See merge request espressif/esp-idf!10833pull/6192/head
Michael (XIAO Xufeng)
commit
eedf2698b6
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@ -7,10 +7,9 @@
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#include "nvs_flash.h"
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#include "driver/timer.h"
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#include "soc/rtc.h"
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#include "soc/soc_caps.h"
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#include "esp_rom_sys.h"
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
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#define TIMER_DIVIDER 16
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#define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) /*!< used to calculate counter value */
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#define TIMER_DELTA 0.001
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@ -38,13 +37,15 @@ static timer_info_t timer_info[4] = {
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TIMER_INFO_INIT(TIMER_GROUP_1, TIMER_1),
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};
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#define GET_TIMER_INFO(TG, TID) (&timer_info[(TG)*2+(TID)])
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static intr_handle_t timer_isr_handles[SOC_TIMER_GROUP_TOTAL_TIMERS];
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#define GET_TIMER_INFO(TG, TID) (&timer_info[(TG)*SOC_TIMER_GROUP_TIMERS_PER_GROUP+(TID)])
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// timer group interruption handle callback
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static bool test_timer_group_isr_cb(void *arg)
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{
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bool is_awoken = false;
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timer_info_t* info = (timer_info_t*) arg;
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timer_info_t *info = (timer_info_t *) arg;
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const timer_group_t timer_group = info->timer_group;
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const timer_idx_t timer_idx = info->timer_idx;
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uint64_t timer_val;
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@ -74,7 +75,9 @@ static bool test_timer_group_isr_cb(void *arg)
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BaseType_t awoken = pdFALSE;
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BaseType_t ret = xQueueSendFromISR(timer_queue, &evt, &awoken);
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TEST_ASSERT_EQUAL(pdTRUE, ret);
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if (awoken) is_awoken = true;
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if (awoken) {
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is_awoken = true;
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}
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}
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return is_awoken;
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}
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@ -90,8 +93,8 @@ static void test_timer_group_isr(void *arg)
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// initialize all timer
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static void all_timer_init(timer_config_t *config, bool expect_init)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ASSERT_EQUAL((expect_init ? ESP_OK : ESP_ERR_INVALID_ARG), timer_init(tg_idx, timer_idx, config));
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}
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}
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@ -103,8 +106,8 @@ static void all_timer_init(timer_config_t *config, bool expect_init)
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// deinitialize all timer
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static void all_timer_deinit(void)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_deinit(tg_idx, timer_idx));
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}
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}
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@ -117,17 +120,17 @@ static void all_timer_deinit(void)
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// start all of timer
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static void all_timer_start(void)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_start(tg_idx, timer_idx));
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_start(tg_idx, timer_idx));
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}
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}
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}
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static void all_timer_set_counter_value(uint64_t set_cnt_val)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_set_counter_value(tg_idx, timer_idx, set_cnt_val));
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}
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}
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@ -135,8 +138,8 @@ static void all_timer_set_counter_value(uint64_t set_cnt_val)
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static void all_timer_pause(void)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_pause(tg_idx, timer_idx));
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}
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}
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@ -146,15 +149,15 @@ static void all_timer_get_counter_value(uint64_t set_cnt_val, bool expect_equal_
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uint64_t *actual_cnt_val)
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{
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uint64_t current_cnt_val;
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_get_counter_value(tg_idx, timer_idx, ¤t_cnt_val));
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if (expect_equal_set_val) {
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TEST_ASSERT_EQUAL(set_cnt_val, current_cnt_val);
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} else {
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TEST_ASSERT_NOT_EQUAL(set_cnt_val, current_cnt_val);
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if (actual_cnt_val != NULL) {
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actual_cnt_val[tg_idx*TIMER_GROUP_MAX + timer_idx] = current_cnt_val;
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actual_cnt_val[tg_idx * SOC_TIMER_GROUP_TIMERS_PER_GROUP + timer_idx] = current_cnt_val;
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}
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}
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}
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@ -164,8 +167,8 @@ static void all_timer_get_counter_value(uint64_t set_cnt_val, bool expect_equal_
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static void all_timer_get_counter_time_sec(int expect_time)
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{
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double time;
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_get_counter_time_sec(tg_idx, timer_idx, &time));
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TEST_ASSERT_FLOAT_WITHIN(TIMER_DELTA, expect_time, time);
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}
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@ -174,8 +177,8 @@ static void all_timer_get_counter_time_sec(int expect_time)
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static void all_timer_set_counter_mode(timer_count_dir_t counter_dir)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_set_counter_mode(tg_idx, timer_idx, counter_dir));
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}
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}
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@ -183,8 +186,8 @@ static void all_timer_set_counter_mode(timer_count_dir_t counter_dir)
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static void all_timer_set_divider(uint32_t divider)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_set_divider(tg_idx, timer_idx, divider));
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}
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}
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@ -192,19 +195,37 @@ static void all_timer_set_divider(uint32_t divider)
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static void all_timer_set_alarm_value(uint64_t alarm_cnt_val)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_set_alarm_value(tg_idx, timer_idx, alarm_cnt_val));
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}
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}
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}
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static void all_timer_get_alarm_value(uint64_t *alarm_vals)
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{
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_get_alarm_value(tg_idx, timer_idx, &alarm_vals[tg_idx * SOC_TIMER_GROUP_TIMERS_PER_GROUP + timer_idx]));
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}
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}
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}
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static void all_timer_isr_reg(void)
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{
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for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(timer_isr_register(tg_idx, timer_idx, test_timer_group_isr,
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GET_TIMER_INFO(tg_idx, timer_idx), ESP_INTR_FLAG_LOWMED, NULL));
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GET_TIMER_INFO(tg_idx, timer_idx), ESP_INTR_FLAG_LOWMED, &timer_isr_handles[tg_idx * SOC_TIMER_GROUP_TIMERS_PER_GROUP + timer_idx]));
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}
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}
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}
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static void all_timer_isr_unreg(void)
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{
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for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
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for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
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TEST_ESP_OK(esp_intr_free(timer_isr_handles[tg_idx * SOC_TIMER_GROUP_TIMERS_PER_GROUP + timer_idx]));
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}
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}
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}
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@ -231,7 +252,7 @@ static void timer_isr_check(timer_group_t group_num, timer_idx_t timer_num, time
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}
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static void timer_intr_enable_disable_test(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_cnt_val)
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{
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{
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alarm_flag = false;
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TEST_ESP_OK(timer_set_counter_value(group_num, timer_num, 0));
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TEST_ESP_OK(timer_set_alarm(group_num, timer_num, TIMER_ALARM_EN));
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@ -287,7 +308,7 @@ TEST_CASE("Timer init", "[hw_timer]")
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};
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all_timer_init(&config3, true);
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timer_config_t get_config;
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TEST_ESP_OK(timer_get_config(TIMER_GROUP_1, TIMER_1, &get_config));
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TEST_ESP_OK(timer_get_config(TIMER_GROUP_1, TIMER_0, &get_config));
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printf("Error config alarm_en is %d\n", get_config.alarm_en);
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TEST_ASSERT_NOT_EQUAL(config3.alarm_en, get_config.alarm_en);
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@ -319,10 +340,10 @@ TEST_CASE("Timer init", "[hw_timer]")
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all_timer_get_counter_value(set_timer_val, false, NULL);
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// Test init 3: wrong parameter
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(-1, TIMER_1, &config));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(-1, TIMER_0, &config));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(TIMER_GROUP_1, 2, &config));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(TIMER_GROUP_1, -1, &config));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(2, TIMER_1, &config));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(2, TIMER_0, &config));
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all_timer_deinit();
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}
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@ -389,8 +410,8 @@ TEST_CASE("Timer start", "[hw_timer]")
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all_timer_get_counter_value(set_timer_val, false, NULL);
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//Test start 2:wrong parameter
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(2, TIMER_1));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(-1, TIMER_1));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(2, TIMER_0));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(-1, TIMER_0));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(TIMER_GROUP_1, 2));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(TIMER_GROUP_1, -1));
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all_timer_deinit();
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@ -531,7 +552,7 @@ TEST_CASE("Timer divider", "[hw_timer]")
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all_timer_get_counter_value(set_timer_val, false, comp_time_val);
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for (i = 0; i < 4; i++) {
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TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]);
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TEST_ASSERT_INT_WITHIN(40000 , 40000000, comp_time_val[i]);
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TEST_ASSERT_INT_WITHIN(40000, 40000000, comp_time_val[i]);
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}
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all_timer_pause();
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@ -542,21 +563,17 @@ TEST_CASE("Timer divider", "[hw_timer]")
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all_timer_get_counter_value(set_timer_val, false, comp_time_val);
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for (i = 0; i < 4; i++) {
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TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]);
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TEST_ASSERT_INT_WITHIN(2 , 1220, comp_time_val[i]);
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TEST_ASSERT_INT_WITHIN(2, 1220, comp_time_val[i]);
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}
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// divider is 1 should be equal with 2
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all_timer_pause();
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_0, TIMER_0, 1));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_1, TIMER_0, 1));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_0, TIMER_1, 1));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_1, TIMER_1, 1));
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all_timer_pause();
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_0, TIMER_0, 65537));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_1, TIMER_0, 65537));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_0, TIMER_1, 65537));
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_1, TIMER_1, 65537));
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all_timer_deinit();
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}
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@ -577,18 +594,18 @@ TEST_CASE("Timer enable alarm", "[hw_timer]")
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};
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all_timer_init(&config_test, true);
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all_timer_isr_reg();
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// enable alarm of tg0_timer1
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alarm_flag = false;
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TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_1, TIMER_ALARM_EN));
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timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 1.2);
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timer_isr_check(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE);
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TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_0, TIMER_ALARM_EN));
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timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 1.2);
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timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE);
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TEST_ASSERT_EQUAL(true, alarm_flag);
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// disable alarm of tg0_timer1
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alarm_flag = false;
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TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_1, TIMER_ALARM_DIS));
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timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 1.2);
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TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_0, TIMER_ALARM_DIS));
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timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 1.2);
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vTaskDelay(2000 / portTICK_PERIOD_MS);
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TEST_ASSERT_EQUAL(false, alarm_flag);
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@ -605,6 +622,7 @@ TEST_CASE("Timer enable alarm", "[hw_timer]")
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timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.2);
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vTaskDelay(2000 / portTICK_PERIOD_MS);
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TEST_ASSERT_EQUAL(false, alarm_flag);
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all_timer_isr_unreg();
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all_timer_deinit();
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}
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@ -615,8 +633,7 @@ TEST_CASE("Timer enable alarm", "[hw_timer]")
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*/
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TEST_CASE("Timer set alarm value", "[hw_timer]")
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{
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int i;
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uint64_t alarm_val[4];
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uint64_t alarm_val[SOC_TIMER_GROUP_TOTAL_TIMERS];
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timer_config_t config = {
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.alarm_en = TIMER_ALARM_EN,
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.auto_reload = TIMER_AUTORELOAD_DIS,
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@ -630,19 +647,17 @@ TEST_CASE("Timer set alarm value", "[hw_timer]")
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// set and get alarm value
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all_timer_set_alarm_value(3 * TIMER_SCALE);
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TEST_ESP_OK(timer_get_alarm_value(TIMER_GROUP_0, TIMER_0, &alarm_val[0]));
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TEST_ESP_OK(timer_get_alarm_value(TIMER_GROUP_0, TIMER_1, &alarm_val[1]));
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TEST_ESP_OK(timer_get_alarm_value(TIMER_GROUP_1, TIMER_0, &alarm_val[2]));
|
||||
TEST_ESP_OK(timer_get_alarm_value(TIMER_GROUP_1, TIMER_1, &alarm_val[3]));
|
||||
for (i = 0; i < 4; i++) {
|
||||
all_timer_get_alarm_value(alarm_val);
|
||||
for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
|
||||
TEST_ASSERT_EQUAL_UINT32(3 * TIMER_SCALE, (uint32_t)alarm_val[i]);
|
||||
}
|
||||
|
||||
// set interrupt read alarm value
|
||||
timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 2.4);
|
||||
timer_isr_check(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_DIS, 2.4 * TIMER_SCALE);
|
||||
timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 2.4);
|
||||
timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_DIS, 2.4 * TIMER_SCALE);
|
||||
timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.4);
|
||||
timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_DIS, 1.4 * TIMER_SCALE);
|
||||
all_timer_isr_unreg();
|
||||
all_timer_deinit();
|
||||
}
|
||||
|
||||
|
|
@ -667,16 +682,12 @@ TEST_CASE("Timer auto reload", "[hw_timer]")
|
|||
// test disable auto_reload
|
||||
timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 1.14);
|
||||
timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_DIS, 1.14 * TIMER_SCALE);
|
||||
timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_1, 1.14);
|
||||
timer_isr_check(TIMER_GROUP_1, TIMER_1, TIMER_AUTORELOAD_DIS, 1.14 * TIMER_SCALE);
|
||||
|
||||
//test enable auto_reload
|
||||
TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_EN));
|
||||
timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 1.4);
|
||||
timer_isr_check(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_EN, 0);
|
||||
TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_EN));
|
||||
timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.4);
|
||||
timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_EN, 0);
|
||||
all_timer_isr_unreg();
|
||||
all_timer_deinit();
|
||||
}
|
||||
|
||||
|
|
@ -702,17 +713,18 @@ TEST_CASE("Timer enable timer interrupt", "[hw_timer]")
|
|||
all_timer_set_counter_value(0);
|
||||
all_timer_isr_reg();
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_0, TIMER_0, 1.2 * TIMER_SCALE);
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_1, 1.2 * TIMER_SCALE);
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_0, 1.2 * TIMER_SCALE);
|
||||
|
||||
// enable interrupt of tg1_timer1 again
|
||||
// enable interrupt of tg1_timer0 again
|
||||
alarm_flag = false;
|
||||
TEST_ESP_OK(timer_pause(TIMER_GROUP_1, TIMER_1));
|
||||
TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_1, TIMER_1, 0));
|
||||
TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_1, TIMER_ALARM_EN));
|
||||
TEST_ESP_OK(timer_enable_intr(TIMER_GROUP_1, TIMER_1));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_1, TIMER_1));
|
||||
timer_isr_check(TIMER_GROUP_1, TIMER_1, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE);
|
||||
TEST_ESP_OK(timer_pause(TIMER_GROUP_1, TIMER_0));
|
||||
TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_1, TIMER_0, 0));
|
||||
TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_0, TIMER_ALARM_EN));
|
||||
TEST_ESP_OK(timer_enable_intr(TIMER_GROUP_1, TIMER_0));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_1, TIMER_0));
|
||||
timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE);
|
||||
TEST_ASSERT_EQUAL(true, alarm_flag);
|
||||
all_timer_isr_unreg();
|
||||
all_timer_deinit();
|
||||
}
|
||||
|
||||
|
|
@ -723,6 +735,7 @@ TEST_CASE("Timer enable timer interrupt", "[hw_timer]")
|
|||
*/
|
||||
TEST_CASE("Timer enable timer group interrupt", "[hw_timer][ignore]")
|
||||
{
|
||||
intr_handle_t isr_handle = NULL;
|
||||
alarm_flag = false;
|
||||
timer_config_t config = {
|
||||
.alarm_en = TIMER_ALARM_EN,
|
||||
|
|
@ -741,7 +754,7 @@ TEST_CASE("Timer enable timer group interrupt", "[hw_timer][ignore]")
|
|||
// enable interrupt of tg0_timer0
|
||||
TEST_ESP_OK(timer_group_intr_enable(TIMER_GROUP_0, TIMER_INTR_T0));
|
||||
TEST_ESP_OK(timer_isr_register(TIMER_GROUP_0, TIMER_0, test_timer_group_isr,
|
||||
GET_TIMER_INFO(TIMER_GROUP_0, TIMER_0), ESP_INTR_FLAG_LOWMED, NULL));
|
||||
GET_TIMER_INFO(TIMER_GROUP_0, TIMER_0), ESP_INTR_FLAG_LOWMED, &isr_handle));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_0));
|
||||
timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE);
|
||||
TEST_ASSERT_EQUAL(true, alarm_flag);
|
||||
|
|
@ -753,13 +766,14 @@ TEST_CASE("Timer enable timer group interrupt", "[hw_timer][ignore]")
|
|||
TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_0));
|
||||
vTaskDelay(2000 / portTICK_PERIOD_MS);
|
||||
TEST_ASSERT_EQUAL(false, alarm_flag);
|
||||
esp_intr_free(isr_handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* isr_register case:
|
||||
* Cycle register 15 times, compare the heap size to ensure no memory leaks
|
||||
*/
|
||||
TEST_CASE("Timer interrupt register", "[hw_timer][leaks=200]")
|
||||
TEST_CASE("Timer interrupt register", "[hw_timer]")
|
||||
{
|
||||
timer_config_t config = {
|
||||
.alarm_en = TIMER_ALARM_DIS,
|
||||
|
|
@ -773,37 +787,37 @@ TEST_CASE("Timer interrupt register", "[hw_timer][leaks=200]")
|
|||
for (int i = 0; i < 15; i++) {
|
||||
all_timer_init(&config, true);
|
||||
timer_isr_handle_t timer_isr_handle[TIMER_GROUP_MAX * TIMER_MAX];
|
||||
for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
|
||||
for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
|
||||
for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
|
||||
for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
|
||||
TEST_ESP_OK(timer_isr_register(tg_idx, timer_idx, test_timer_group_isr,
|
||||
GET_TIMER_INFO(tg_idx, timer_idx), ESP_INTR_FLAG_LOWMED, &timer_isr_handle[tg_idx * TIMER_GROUP_MAX + timer_idx]));
|
||||
GET_TIMER_INFO(tg_idx, timer_idx), ESP_INTR_FLAG_LOWMED, &timer_isr_handle[tg_idx * SOC_TIMER_GROUP_TIMERS_PER_GROUP + timer_idx]));
|
||||
}
|
||||
}
|
||||
|
||||
TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_0, TIMER_ALARM_EN));
|
||||
timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 0.54);
|
||||
TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_1, TIMER_ALARM_EN));
|
||||
timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_1, 0.34);
|
||||
TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_0, TIMER_ALARM_EN));
|
||||
timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 0.34);
|
||||
|
||||
TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_EN));
|
||||
TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_1, TIMER_ALARM_EN));
|
||||
timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 0.4);
|
||||
TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_EN));
|
||||
TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_0, TIMER_ALARM_EN));
|
||||
timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 0.4);
|
||||
TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_EN));
|
||||
TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_0, TIMER_ALARM_EN));
|
||||
timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 0.6);
|
||||
vTaskDelay(1000 / portTICK_PERIOD_MS);
|
||||
|
||||
// ISR hanlde function should be free before next ISR register.
|
||||
for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) {
|
||||
for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) {
|
||||
TEST_ESP_OK(esp_intr_free(timer_isr_handle[tg_idx * TIMER_GROUP_MAX + timer_idx]));
|
||||
for (uint32_t tg_idx = 0; tg_idx < TIMER_GROUP_MAX; tg_idx++) {
|
||||
for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
|
||||
TEST_ESP_OK(esp_intr_free(timer_isr_handle[tg_idx * SOC_TIMER_GROUP_TIMERS_PER_GROUP + timer_idx]));
|
||||
}
|
||||
}
|
||||
all_timer_deinit();
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
|
||||
#if SOC_TIMER_GROUP_SUPPORT_XTAL
|
||||
/**
|
||||
* Timer clock source:
|
||||
* 1. configure clock source as APB clock, and enable timer interrupt
|
||||
|
|
@ -829,7 +843,7 @@ TEST_CASE("Timer clock source", "[hw_timer]")
|
|||
all_timer_isr_reg();
|
||||
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_0, TIMER_0, 1.2 * timer_scale);
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_1, 1.2 * timer_scale );
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_0, 1.2 * timer_scale );
|
||||
|
||||
// configure clock source as XTAL clock
|
||||
all_timer_pause();
|
||||
|
|
@ -839,8 +853,9 @@ TEST_CASE("Timer clock source", "[hw_timer]")
|
|||
all_timer_set_alarm_value(1.2 * timer_scale);
|
||||
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_0, TIMER_0, 1.2 * timer_scale);
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_1, 1.2 * timer_scale );
|
||||
timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_0, 1.2 * timer_scale );
|
||||
|
||||
all_timer_isr_unreg();
|
||||
all_timer_deinit();
|
||||
}
|
||||
#endif
|
||||
|
|
@ -867,27 +882,27 @@ TEST_CASE("Timer ISR callback", "[hw_timer]")
|
|||
all_timer_set_alarm_value(alarm_cnt_val);
|
||||
all_timer_set_counter_value(set_timer_val);
|
||||
|
||||
// add isr callback for tg0_timer1
|
||||
TEST_ESP_OK(timer_isr_callback_add(TIMER_GROUP_0, TIMER_1, test_timer_group_isr_cb,
|
||||
GET_TIMER_INFO(TIMER_GROUP_0, TIMER_1), ESP_INTR_FLAG_LOWMED));
|
||||
TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_0, TIMER_1, set_timer_val));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_1));
|
||||
timer_isr_check(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_DIS, alarm_cnt_val);
|
||||
// add isr callback for tg0_timer0
|
||||
TEST_ESP_OK(timer_isr_callback_add(TIMER_GROUP_0, TIMER_0, test_timer_group_isr_cb,
|
||||
GET_TIMER_INFO(TIMER_GROUP_0, TIMER_0), ESP_INTR_FLAG_LOWMED));
|
||||
TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_0, TIMER_0, set_timer_val));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_0));
|
||||
timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_DIS, alarm_cnt_val);
|
||||
TEST_ASSERT_EQUAL(true, alarm_flag);
|
||||
|
||||
// remove isr callback for tg0_timer1
|
||||
TEST_ESP_OK(timer_pause(TIMER_GROUP_0, TIMER_1));
|
||||
TEST_ESP_OK(timer_isr_callback_remove(TIMER_GROUP_0, TIMER_1));
|
||||
// remove isr callback for tg0_timer0
|
||||
TEST_ESP_OK(timer_pause(TIMER_GROUP_0, TIMER_0));
|
||||
TEST_ESP_OK(timer_isr_callback_remove(TIMER_GROUP_0, TIMER_0));
|
||||
alarm_flag = false;
|
||||
TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_0, TIMER_1, set_timer_val));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_1));
|
||||
TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_0, TIMER_0, set_timer_val));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_0));
|
||||
vTaskDelay(2000 / portTICK_PERIOD_MS);
|
||||
TEST_ASSERT_EQUAL(false, alarm_flag);
|
||||
|
||||
// add isr callback for tg1_timer0
|
||||
TEST_ESP_OK(timer_pause(TIMER_GROUP_1, TIMER_0));
|
||||
TEST_ESP_OK(timer_isr_callback_add(TIMER_GROUP_1, TIMER_0, test_timer_group_isr_cb,
|
||||
GET_TIMER_INFO(TIMER_GROUP_1, TIMER_0), ESP_INTR_FLAG_LOWMED));
|
||||
GET_TIMER_INFO(TIMER_GROUP_1, TIMER_0), ESP_INTR_FLAG_LOWMED));
|
||||
TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_1, TIMER_0, set_timer_val));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_1, TIMER_0));
|
||||
timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_DIS, alarm_cnt_val);
|
||||
|
|
@ -907,7 +922,7 @@ TEST_CASE("Timer ISR callback", "[hw_timer]")
|
|||
/**
|
||||
* Timer memory test
|
||||
*/
|
||||
TEST_CASE("Timer memory test", "[hw_timer][leaks=100]")
|
||||
TEST_CASE("Timer memory test", "[hw_timer]")
|
||||
{
|
||||
timer_config_t config = {
|
||||
.alarm_en = TIMER_ALARM_EN,
|
||||
|
|
@ -917,7 +932,7 @@ TEST_CASE("Timer memory test", "[hw_timer][leaks=100]")
|
|||
.counter_en = TIMER_PAUSE,
|
||||
.intr_type = TIMER_INTR_LEVEL,
|
||||
};
|
||||
for(uint32_t i=0; i<100; i++) {
|
||||
for (uint32_t i = 0; i < 100; i++) {
|
||||
all_timer_init(&config, true);
|
||||
all_timer_deinit();
|
||||
}
|
||||
|
|
@ -955,7 +970,7 @@ static void timer_group_test_first_stage(void)
|
|||
TEST_ESP_OK(timer_enable_intr(TIMER_GROUP_0, TIMER_0));
|
||||
TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_0));
|
||||
//Waiting for timer_group to generate an interrupt
|
||||
while( !(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) &&
|
||||
while ( !(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) &&
|
||||
loop_cnt++ < 100) {
|
||||
vTaskDelay(200);
|
||||
}
|
||||
|
|
@ -972,8 +987,6 @@ static void timer_group_test_second_stage(void)
|
|||
}
|
||||
|
||||
TEST_CASE_MULTIPLE_STAGES("timer_group software reset test",
|
||||
"[intr_status][intr_status = 0]",
|
||||
timer_group_test_first_stage,
|
||||
timer_group_test_second_stage);
|
||||
|
||||
#endif
|
||||
"[intr_status][intr_status = 0]",
|
||||
timer_group_test_first_stage,
|
||||
timer_group_test_second_stage);
|
||||
|
|
|
|||
|
|
@ -17,10 +17,10 @@
|
|||
#include "esp_err.h"
|
||||
#include "esp_intr_alloc.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/xtensa_api.h"
|
||||
#include "driver/timer.h"
|
||||
#include "driver/periph_ctrl.h"
|
||||
#include "hal/timer_hal.h"
|
||||
#include "soc/timer_periph.h"
|
||||
#include "soc/rtc.h"
|
||||
|
||||
static const char *TIMER_TAG = "timer_group";
|
||||
|
|
@ -83,7 +83,7 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
|
|||
uint32_t div;
|
||||
timer_hal_get_divider(&(p_timer_obj[group_num][timer_num]->hal), &div);
|
||||
*time = (double)timer_val * div / rtc_clk_apb_freq_get();
|
||||
#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
|
||||
#if SOC_TIMER_GROUP_SUPPORT_XTAL
|
||||
if (timer_hal_get_use_xtal(&(p_timer_obj[group_num][timer_num]->hal))) {
|
||||
*time = (double)timer_val * div / ((int)rtc_clk_xtal_freq_get() * 1000000);
|
||||
}
|
||||
|
|
@ -266,36 +266,10 @@ esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num,
|
|||
TIMER_CHECK(fn != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
|
||||
TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
|
||||
|
||||
int intr_source = 0;
|
||||
uint32_t status_reg = 0;
|
||||
uint32_t mask = 0;
|
||||
switch (group_num) {
|
||||
case TIMER_GROUP_0:
|
||||
default:
|
||||
intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer_num;
|
||||
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
|
||||
if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE)) {
|
||||
intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer_num;
|
||||
}
|
||||
#endif
|
||||
timer_hal_get_status_reg_mask_bit(&(p_timer_obj[TIMER_GROUP_0][timer_num]->hal), &status_reg, &mask);
|
||||
break;
|
||||
case TIMER_GROUP_1:
|
||||
intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num;
|
||||
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
|
||||
if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE)) {
|
||||
intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer_num;
|
||||
}
|
||||
#endif
|
||||
if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE) == 0) {
|
||||
intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num;
|
||||
} else {
|
||||
intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num;
|
||||
}
|
||||
timer_hal_get_status_reg_mask_bit(&(p_timer_obj[TIMER_GROUP_1][timer_num]->hal), &status_reg, &mask);
|
||||
break;
|
||||
}
|
||||
return esp_intr_alloc_intrstatus(intr_source, intr_alloc_flags, status_reg, mask, fn, arg, handle);
|
||||
timer_hal_get_status_reg_mask_bit(&(p_timer_obj[group_num][timer_num]->hal), &status_reg, &mask);
|
||||
return esp_intr_alloc_intrstatus(timer_group_periph_signals.groups[group_num].t0_irq_id + timer_num, intr_alloc_flags, status_reg, mask, fn, arg, handle);
|
||||
}
|
||||
|
||||
esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t *config)
|
||||
|
|
@ -305,11 +279,7 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
|
|||
TIMER_CHECK(config != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
|
||||
TIMER_CHECK(config->divider > 1 && config->divider < 65537, DIVIDER_RANGE_ERROR, ESP_ERR_INVALID_ARG);
|
||||
|
||||
if (group_num == TIMER_GROUP_0) {
|
||||
periph_module_enable(PERIPH_TIMG0_MODULE);
|
||||
} else if (group_num == TIMER_GROUP_1) {
|
||||
periph_module_enable(PERIPH_TIMG1_MODULE);
|
||||
}
|
||||
periph_module_enable(timer_group_periph_signals.groups[group_num].module);
|
||||
|
||||
if (p_timer_obj[group_num][timer_num] == NULL) {
|
||||
p_timer_obj[group_num][timer_num] = (timer_obj_t *) heap_caps_calloc(1, sizeof(timer_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
|
||||
|
|
@ -327,15 +297,12 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
|
|||
timer_hal_set_divider(&(p_timer_obj[group_num][timer_num]->hal), config->divider);
|
||||
timer_hal_set_counter_increase(&(p_timer_obj[group_num][timer_num]->hal), config->counter_dir);
|
||||
timer_hal_set_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal), config->alarm_en);
|
||||
if (config->intr_type == TIMER_INTR_LEVEL) {
|
||||
timer_hal_set_level_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
|
||||
timer_hal_set_level_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
|
||||
if (config->intr_type != TIMER_INTR_LEVEL) {
|
||||
ESP_LOGW(TIMER_TAG, "only support Level Interrupt, switch to Level Interrupt instead");
|
||||
}
|
||||
// currently edge interrupt is not supported
|
||||
// if (config->intr_type == TIMER_INTR_EDGE) {
|
||||
// timer_hal_set_edge_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
|
||||
// }
|
||||
timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), config->counter_en);
|
||||
#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
|
||||
#if SOC_TIMER_GROUP_SUPPORT_XTAL
|
||||
timer_hal_set_use_xtal(&(p_timer_obj[group_num][timer_num]->hal), config->clk_src);
|
||||
#endif
|
||||
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
|
||||
|
|
@ -450,9 +417,12 @@ uint32_t IRAM_ATTR timer_group_get_intr_status_in_isr(timer_group_t group_num)
|
|||
uint32_t intr_status = 0;
|
||||
if (p_timer_obj[group_num][TIMER_0] != NULL) {
|
||||
timer_hal_get_intr_status(&(p_timer_obj[group_num][TIMER_0]->hal), &intr_status);
|
||||
} else if (p_timer_obj[group_num][TIMER_1] != NULL) {
|
||||
}
|
||||
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
|
||||
else if (p_timer_obj[group_num][TIMER_1] != NULL) {
|
||||
timer_hal_get_intr_status(&(p_timer_obj[group_num][TIMER_1]->hal), &intr_status);
|
||||
}
|
||||
#endif
|
||||
return intr_status;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -302,7 +302,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
|
|||
*/
|
||||
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
|
||||
{
|
||||
*intr_status = hw->int_st_timers.val;
|
||||
*intr_status = hw->int_st_timers.val & 0x03;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -316,7 +316,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
|
|||
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
|
||||
{
|
||||
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
|
||||
*intr_raw_status = hw->int_raw.val;
|
||||
*intr_raw_status = hw->int_raw.val & 0x03;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -298,7 +298,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
|
|||
*/
|
||||
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
|
||||
{
|
||||
*intr_status = hw->int_st.val;
|
||||
*intr_status = hw->int_st.val & 0x03;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -312,7 +312,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
|
|||
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
|
||||
{
|
||||
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
|
||||
*intr_raw_status = hw->int_raw.val;
|
||||
*intr_raw_status = hw->int_raw.val & 0x03;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -297,7 +297,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
|
|||
*/
|
||||
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
|
||||
{
|
||||
*intr_status = hw->int_st.val;
|
||||
*intr_status = hw->int_st.val & 0x03;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -311,7 +311,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
|
|||
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
|
||||
{
|
||||
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
|
||||
*intr_raw_status = hw->int_raw.val;
|
||||
*intr_raw_status = hw->int_raw.val & 0x03;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,7 +29,9 @@ extern "C" {
|
|||
*/
|
||||
typedef enum {
|
||||
TIMER_GROUP_0 = 0, /*!<Hw timer group 0*/
|
||||
#if SOC_TIMER_GROUPS > 1
|
||||
TIMER_GROUP_1 = 1, /*!<Hw timer group 1*/
|
||||
#endif
|
||||
TIMER_GROUP_MAX,
|
||||
} timer_group_t;
|
||||
|
||||
|
|
@ -38,7 +40,9 @@ typedef enum {
|
|||
*/
|
||||
typedef enum {
|
||||
TIMER_0 = 0, /*!<Select timer0 of GROUPx*/
|
||||
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
|
||||
TIMER_1 = 1, /*!<Select timer1 of GROUPx*/
|
||||
#endif
|
||||
TIMER_MAX,
|
||||
} timer_idx_t;
|
||||
|
||||
|
|
@ -64,9 +68,13 @@ typedef enum {
|
|||
*/
|
||||
//this is compatible with the value of esp32.
|
||||
typedef enum {
|
||||
TIMER_INTR_T0 = BIT(0), /*!< interrupt of timer 0 */
|
||||
TIMER_INTR_T1 = BIT(1), /*!< interrupt of timer 1 */
|
||||
TIMER_INTR_T0 = BIT(0), /*!< interrupt of timer 0 */
|
||||
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
|
||||
TIMER_INTR_T1 = BIT(1), /*!< interrupt of timer 1 */
|
||||
TIMER_INTR_WDT = BIT(2), /*!< interrupt of watchdog */
|
||||
#else
|
||||
TIMER_INTR_WDT = BIT(1), /*!< interrupt of watchdog */
|
||||
#endif
|
||||
TIMER_INTR_NONE = 0
|
||||
} timer_intr_t;
|
||||
FLAG_ATTR(timer_intr_t)
|
||||
|
|
@ -85,7 +93,6 @@ typedef enum {
|
|||
*/
|
||||
typedef enum {
|
||||
TIMER_INTR_LEVEL = 0, /*!< Interrupt mode: level mode*/
|
||||
//TIMER_INTR_EDGE = 1, /*!< Interrupt mode: edge mode, Not supported Now*/
|
||||
TIMER_INTR_MAX
|
||||
} timer_intr_mode_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ set(srcs
|
|||
"sigmadelta_periph.c"
|
||||
"soc_memory_layout.c"
|
||||
"spi_periph.c"
|
||||
"timer_periph.c"
|
||||
"touch_sensor_periph.c"
|
||||
"uart_periph.c")
|
||||
|
||||
|
|
|
|||
|
|
@ -186,7 +186,11 @@
|
|||
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 0
|
||||
|
||||
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
|
||||
// No contents here
|
||||
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
|
||||
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
|
||||
#define SOC_TIMER_GROUPS (2)
|
||||
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
|
||||
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
|
||||
|
||||
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
||||
#define SOC_TOUCH_SENSOR_NUM (10)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,29 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/timer_periph.h"
|
||||
|
||||
const timer_group_signal_conn_t timer_group_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module = PERIPH_TIMG0_MODULE,
|
||||
.t0_irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE
|
||||
},
|
||||
[1] = {
|
||||
.module = PERIPH_TIMG1_MODULE,
|
||||
.t0_irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
@ -13,6 +13,7 @@ set(srcs
|
|||
"sigmadelta_periph.c"
|
||||
"soc_memory_layout.c"
|
||||
"spi_periph.c"
|
||||
"timer_periph.c"
|
||||
"touch_sensor_periph.c"
|
||||
"uart_periph.c"
|
||||
"usb_periph.c")
|
||||
|
|
|
|||
|
|
@ -190,7 +190,12 @@
|
|||
#define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part
|
||||
|
||||
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL 1
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
||||
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
|
||||
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
|
||||
#define SOC_TIMER_GROUPS (2)
|
||||
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
|
||||
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
|
||||
|
||||
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
||||
#define SOC_TOUCH_SENSOR_NUM (15) /*! 15 Touch channels */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
|
|
@ -12,6 +12,17 @@
|
|||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include "soc/timer_periph.h"
|
||||
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL 1
|
||||
const timer_group_signal_conn_t timer_group_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module = PERIPH_TIMG0_MODULE,
|
||||
.t0_irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE
|
||||
},
|
||||
[1] = {
|
||||
.module = PERIPH_TIMG1_MODULE,
|
||||
.t0_irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
@ -15,6 +15,7 @@ set(srcs
|
|||
"sigmadelta_periph.c"
|
||||
"soc_memory_layout.c"
|
||||
"spi_periph.c"
|
||||
"timer_periph.c"
|
||||
"touch_sensor_periph.c"
|
||||
"uart_periph.c")
|
||||
|
||||
|
|
|
|||
|
|
@ -69,7 +69,12 @@
|
|||
#include "systimer_caps.h"
|
||||
|
||||
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
|
||||
#include "timer_group_caps.h"
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
||||
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
|
||||
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
|
||||
#define SOC_TIMER_GROUPS (2)
|
||||
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
|
||||
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
|
||||
|
||||
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
||||
#include "touch_sensor_caps.h"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "soc/timer_periph.h"
|
||||
|
||||
const timer_group_signal_conn_t timer_group_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module = PERIPH_TIMG0_MODULE,
|
||||
.t0_irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE
|
||||
},
|
||||
[1] = {
|
||||
.module = PERIPH_TIMG1_MODULE,
|
||||
.t0_irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
@ -13,5 +13,26 @@
|
|||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/timer_group_reg.h"
|
||||
#include "soc/timer_group_struct.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/periph_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
struct {
|
||||
const periph_module_t module; // Peripheral module
|
||||
const int t0_irq_id; // Interrupt ID of the first timer in the group
|
||||
} groups[SOC_TIMER_GROUPS];
|
||||
} timer_group_signal_conn_t;
|
||||
|
||||
extern const timer_group_signal_conn_t timer_group_periph_signals;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue