diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 339de24e05..7ac1e9cba1 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -16,7 +16,7 @@ if(${target} STREQUAL "esp32c6") list(APPEND priv_requires hal) endif() -set(srcs "cpu.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c") +set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c") if(NOT BOOTLOADER_BUILD) list(APPEND srcs "esp_clk.c" "clk_ctrl_os.c" diff --git a/components/esp_hw_support/cpu.c b/components/esp_hw_support/cpu.c index b1f457a4b4..6cbcc64a3b 100644 --- a/components/esp_hw_support/cpu.c +++ b/components/esp_hw_support/cpu.c @@ -149,184 +149,6 @@ void esp_cpu_wait_for_intr(void) #endif // __XTENSA__ } -/* -------------------------------------------------- CPU Registers ---------------------------------------------------- - * - * ------------------------------------------------------------------------------------------------------------------ */ - -/* ------------------------------------------------- CPU Interrupts ---------------------------------------------------- - * - * ------------------------------------------------------------------------------------------------------------------ */ - -// ---------------- Interrupt Descriptors ------------------ - -#if SOC_CPU_HAS_FLEXIBLE_INTC - - -#if SOC_INT_CLIC_SUPPORTED - -static bool is_intr_num_resv(int ext_intr_num) { - /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software - * interrupts, all the other lines starting from 16 and above can be used by external peripheral. - * in the case of this function, the parameter only refers to the external peripheral index, so if - * `ext_intr_num` is 0, it refers to interrupt index 16. - * - * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */ - return ext_intr_num == 6; -} - -#else // !SOC_INT_CLIC_SUPPORTED - -static bool is_intr_num_resv(int intr_num) -{ - // Workaround to reserve interrupt number 1 for Wi-Fi, 5,8 for Bluetooth, 6 for "permanently disabled interrupt" - // [TODO: IDF-2465] - uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8); - - // int_num 0,3,4,7 are unavailable for PULP cpu -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2// TODO: IDF-5728 replace with a better macro name - reserved |= BIT(0) | BIT(3) | BIT(4) | BIT(7); -#endif - - if (reserved & BIT(intr_num)) { - return true; - } - - extern int _vector_table; - extern int _interrupt_handler; - const intptr_t pc = (intptr_t)(&_vector_table + intr_num); - - /* JAL instructions are relative to the PC there are executed from. */ - const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc); - - return destination != (intptr_t)&_interrupt_handler; -} - -#endif // SOC_INT_CLIC_SUPPORTED - -void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) -{ - intr_desc_ret->priority = 1; //Todo: We should make this -1 - intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; -#if __riscv - intr_desc_ret->flags = is_intr_num_resv(intr_num) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0; -#else - intr_desc_ret->flags = 0; -#endif -} - -#else // SOC_CPU_HAS_FLEXIBLE_INTC - -typedef struct { - int priority; - esp_cpu_intr_type_t type; - uint32_t flags[SOC_CPU_CORES_NUM]; -} intr_desc_t; - -#if SOC_CPU_CORES_NUM > 1 -// Note: We currently only have dual core targets, so the table initializer is hard coded -const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //0 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //1 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //2 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //3 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //4 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //5 -#if CONFIG_FREERTOS_CORETIMER_0 - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //6 -#else - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //6 -#endif - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //7 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //8 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //9 - { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, //10 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //11 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0} }, //12 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0} }, //13 - { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //14, NMI -#if CONFIG_FREERTOS_CORETIMER_1 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //15 -#else - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //15 -#endif - { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //16 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //17 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //18 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //19 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //20 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //21 - { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //22 - { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //23 - { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //24 - { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //25 - { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //26 - { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //27 - { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, //28 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //29 - { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //30 - { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //31 -}; - -#else // SOC_CPU_CORES_NUM > 1 - -const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //0 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //1 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //2 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //3 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //4 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //5 -#if CONFIG_FREERTOS_CORETIMER_0 - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //6 -#else - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //6 -#endif - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //7 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //8 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //9 - { 1, ESP_CPU_INTR_TYPE_EDGE, { 0 } }, //10 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //11 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //12 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //13 - { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //14, NMI -#if CONFIG_FREERTOS_CORETIMER_1 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //15 -#else - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //15 -#endif - { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //16 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //17 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //18 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //19 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //20 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //21 - { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //22 - { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //23 - { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //24 - { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //25 - { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //26 - { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //27 - { 4, ESP_CPU_INTR_TYPE_EDGE, { 0 } }, //28 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //29 - { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //30 - { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //31 -}; - -#endif // SOC_CPU_CORES_NUM > 1 - -void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) -{ - assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM); -#if SOC_CPU_CORES_NUM == 1 - core_id = 0; //If this is a single core target, hard code CPU ID to 0 -#endif - intr_desc_ret->priority = intr_desc_table[intr_num].priority; - intr_desc_ret->type = intr_desc_table[intr_num].type; - intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id]; -} - -#endif // SOC_CPU_HAS_FLEXIBLE_INTC - /* ---------------------------------------------------- Debugging ------------------------------------------------------ * * ------------------------------------------------------------------------------------------------------------------ */ diff --git a/components/esp_hw_support/include/esp_private/esp_riscv_intr.h b/components/esp_hw_support/include/esp_private/esp_riscv_intr.h new file mode 100644 index 0000000000..e2d6b479a7 --- /dev/null +++ b/components/esp_hw_support/include/esp_private/esp_riscv_intr.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include + +#if CONFIG_IDF_TARGET_ARCH_RISCV + +#include "esp_cpu.h" +#include "riscv/instruction_decode.h" + +/** + * @brief Checks whether the given interrupt number is reserved either in the given mask or in the + * _vector_table, which contains the routines the CPU will jump to when an interrupt or an exception + * occurs, on RISC-V targets. + * + * @param intr_num Interrupt number to check, in range 0~32 + * @param rsvd_mask Reserved interrupt mask, where bit i is 1 if interrupt i is reserved. + * + * @returns ESP_CPU_INTR_DESC_FLAG_RESVD if the interrupt is reserved, 0 else + */ +static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask) +{ + if (rsvd_mask & BIT(intr_num)) { + return ESP_CPU_INTR_DESC_FLAG_RESVD; + } + + extern int _vector_table; + extern int _interrupt_handler; + const intptr_t pc = (intptr_t)(&_vector_table + intr_num); + + /* JAL instructions are relative to the PC they are executed from. */ + const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc); + + return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0; +} + +#endif // CONFIG_IDF_TARGET_ARCH_RISCV diff --git a/components/esp_hw_support/port/esp32/esp_cpu_intr.c b/components/esp_hw_support/port/esp32/esp_cpu_intr.c new file mode 100644 index 0000000000..d80a1f6d74 --- /dev/null +++ b/components/esp_hw_support/port/esp32/esp_cpu_intr.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "esp_cpu.h" + +/* Xtensa core has 3 interrupts dedicated to timers, we can use either timer0 or timer1 depending on the Kconfig, + * timer2 is always set to SPECIAL in our configuration array */ + +/** + * @brief Type defined for the table below + */ +typedef struct { + int priority; + esp_cpu_intr_type_t type; + uint32_t flags[SOC_CPU_CORES_NUM]; +} intr_desc_t; + + +const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { + [0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, + [5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, +#if CONFIG_FREERTOS_CORETIMER_0 + [6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, +#else + [6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, +#endif + [7] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [10] = { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI +#if CONFIG_FREERTOS_CORETIMER_1 + [15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, +#else + [15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, +#endif + [16] = { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, + [23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, + [25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [29] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, +}; + + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM && intr_desc_ret != NULL); + intr_desc_ret->priority = intr_desc_table[intr_num].priority; + intr_desc_ret->type = intr_desc_table[intr_num].type; + intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id]; +} diff --git a/components/esp_hw_support/port/esp32c2/esp_cpu_intr.c b/components/esp_hw_support/port/esp32c2/esp_cpu_intr.c new file mode 100644 index 0000000000..04704f03f0 --- /dev/null +++ b/components/esp_hw_support/port/esp32c2/esp_cpu_intr.c @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-C2, interrupt: + * - 1 is for Wi-Fi + * - 5 and 8 for Bluetooth + * - 6 for "permanently disabled interrupt" + */ + // [TODO: IDF-2465] + const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32c3/esp_cpu_intr.c b/components/esp_hw_support/port/esp32c3/esp_cpu_intr.c new file mode 100644 index 0000000000..9d835163fd --- /dev/null +++ b/components/esp_hw_support/port/esp32c3/esp_cpu_intr.c @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-C3, interrupt: + * - 1 is for Wi-Fi + * - 5 and 8 for Bluetooth + * - 6 for "permanently disabled interrupt" + */ + // [TODO: IDF-2465] + const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32c5/esp_cpu_intr.c b/components/esp_hw_support/port/esp32c5/esp_cpu_intr.c new file mode 100644 index 0000000000..051bb2128b --- /dev/null +++ b/components/esp_hw_support/port/esp32c5/esp_cpu_intr.c @@ -0,0 +1,20 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software + * interrupts, all the other lines starting from 16 and above can be used by external peripheral. + * + * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */ + /* TODO: IDF-8655, we may need to reserve more interrupts once we have Wifi and BT */ + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0; +} diff --git a/components/esp_hw_support/port/esp32c6/esp_cpu_intr.c b/components/esp_hw_support/port/esp32c6/esp_cpu_intr.c new file mode 100644 index 0000000000..04dfbedadc --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/esp_cpu_intr.c @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-C6, interrupt: + * - 1 is for Wi-Fi + * - 5 and 8 for Bluetooth + * - 6 for "permanently disabled interrupt" + * + * Interrupts 0, 3, 4 and 7 are unavailable for PULP CPU. + */ + // [TODO: IDF-2465] + const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) | + BIT(5) | BIT(6) | BIT(7) | BIT(8); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c b/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c new file mode 100644 index 0000000000..77a24707e8 --- /dev/null +++ b/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-H2, interrupt: + * - 1 is for Wi-Fi + * - 5 and 8 for Bluetooth + * - 6 for "permanently disabled interrupt" + * + * Interrupts 0, 3, 4 and 7 are unavailable for PULP CPU. + */ + // [TODO: IDF-2465] + const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) | + BIT(5) | BIT(6) | BIT(7) | BIT(8); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32p4/esp_cpu_intr.c b/components/esp_hw_support/port/esp32p4/esp_cpu_intr.c new file mode 100644 index 0000000000..84e50b9e67 --- /dev/null +++ b/components/esp_hw_support/port/esp32p4/esp_cpu_intr.c @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software + * interrupts, all the other lines starting from 16 and above can be used by external peripheral. + * + * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */ + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0; +} diff --git a/components/esp_hw_support/port/esp32s2/esp_cpu_intr.c b/components/esp_hw_support/port/esp32s2/esp_cpu_intr.c new file mode 100644 index 0000000000..d34701106c --- /dev/null +++ b/components/esp_hw_support/port/esp32s2/esp_cpu_intr.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "esp_cpu.h" + +/* Xtensa core has 3 interrupts dedicated to timers, we can use either timer0 or timer1 depending on the Kconfig, + * timer2 is always set to SPECIAL in our configuration array */ + +/** + * @brief Type defined for the table below + */ +typedef struct { + int priority; + esp_cpu_intr_type_t type; + uint32_t flags; +} intr_desc_t; + + +const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { + [0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, +#if CONFIG_FREERTOS_CORETIMER_0 + [6] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD }, +#else + [6] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, +#endif + [7] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, + [8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [10] = { 1, ESP_CPU_INTR_TYPE_EDGE, 0 }, + [11] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, + [12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, // NMI +#if CONFIG_FREERTOS_CORETIMER_1 + [15] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD }, +#else + [15] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, +#endif + [16] = { 5, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, + [17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [22] = { 3, ESP_CPU_INTR_TYPE_EDGE, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [28] = { 4, ESP_CPU_INTR_TYPE_EDGE, 0 }, + [29] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, + [30] = { 4, ESP_CPU_INTR_TYPE_EDGE, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, +}; + + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + assert(core_id == 0 && intr_num < SOC_CPU_INTR_NUM && intr_desc_ret != NULL); + intr_desc_ret->priority = intr_desc_table[intr_num].priority; + intr_desc_ret->type = intr_desc_table[intr_num].type; + intr_desc_ret->flags = intr_desc_table[intr_num].flags; +} diff --git a/components/esp_hw_support/port/esp32s3/esp_cpu_intr.c b/components/esp_hw_support/port/esp32s3/esp_cpu_intr.c new file mode 100644 index 0000000000..1d7f03f7ad --- /dev/null +++ b/components/esp_hw_support/port/esp32s3/esp_cpu_intr.c @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include "esp_cpu.h" + +/* The ESP32-S3 uses the SysTimer for the FreeRTOS system tick, there is no need to Xtensa core interrupts, + * which will be marked as ESP_CPU_INTR_DESC_FLAG_SPECIAL */ + +/** + * @brief Type defined for the table below + */ +typedef struct { + int priority; + esp_cpu_intr_type_t type; + uint32_t flags[SOC_CPU_CORES_NUM]; +} intr_desc_t; + + +const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { + [0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, + [5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [7] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [10] = { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI + [15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [16] = { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, + [23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, + [25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [29] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, +}; + + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM && intr_desc_ret != NULL); + intr_desc_ret->priority = intr_desc_table[intr_num].priority; + intr_desc_ret->type = intr_desc_table[intr_num].type; + intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id]; +}