kopia lustrzana https://github.com/espressif/esp-idf
change(ble): support ble light sleep using ext 32k xtal on C2
rodzic
5e443311da
commit
edb3f70562
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@ -421,6 +421,26 @@ config BT_LE_SLEEP_ENABLE
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help
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Enable BLE sleep
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choice BT_LE_LP_CLK_SRC
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prompt "BLE low power clock source"
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default BT_LE_LP_CLK_SRC_MAIN_XTAL
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config BT_LE_LP_CLK_SRC_MAIN_XTAL
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bool "Use main XTAL as RTC clock source"
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help
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User main XTAL as RTC clock source.
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This option is recommended if external 32.768k XTAL is not available.
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Using the external 32.768 kHz XTAL will have lower current consumption
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in light sleep compared to using the main XTAL.
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config BT_LE_LP_CLK_SRC_DEFAULT
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bool "Use system RTC slow clock source"
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help
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Use the same slow clock source as system RTC
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Using any clock source other than external 32.768 kHz XTAL at pin0 supports only
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legacy ADV and SCAN due to low clock accuracy.
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endchoice
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config BT_LE_USE_ESP_TIMER
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bool "Use Esp Timer for callout"
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depends on !BT_NIMBLE_ENABLED
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -54,12 +54,14 @@
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#include "freertos/task.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_clk.h"
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#include "esp_sleep.h"
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#include "soc/syscon_reg.h"
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#include "soc/dport_access.h"
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#include "hal/efuse_ll.h"
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#include "soc/rtc.h"
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/* Macro definition
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************************************************************************
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*/
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@ -78,6 +80,11 @@
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#define ACL_DATA_MBUF_LEADINGSPCAE 4
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#endif // CONFIG_BT_BLUEDROID_ENABLED
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typedef enum ble_rtc_slow_clk_src {
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BT_SLOW_CLK_SRC_MAIN_XTAL,
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BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0,
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} ble_rtc_slow_clk_src_t;
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/* Types definition
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************************************************************************
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*/
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@ -487,7 +494,7 @@ IRAM_ATTR void controller_wakeup_cb(void *arg)
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s_ble_active = true;
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}
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esp_err_t controller_sleep_init(void)
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esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src)
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{
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esp_err_t rc = 0;
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#ifdef CONFIG_BT_LE_SLEEP_ENABLE
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@ -495,7 +502,11 @@ esp_err_t controller_sleep_init(void)
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r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US);
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#ifdef CONFIG_PM_ENABLE
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esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
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if (slow_clk_src == BT_SLOW_CLK_SRC_MAIN_XTAL) {
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esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
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} else {
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esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
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}
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#endif // CONFIG_PM_ENABLE
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#endif // CONFIG_BT_LE_SLEEP_ENABLE
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@ -546,37 +557,74 @@ void controller_sleep_deinit(void)
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#endif //CONFIG_PM_ENABLE
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}
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void ble_rtc_clk_init(void)
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static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
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{
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// modem_clkrst_reg
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// LP_TIMER_SEL_XTAL32K -> 0
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// LP_TIMER_SEL_XTAL -> 1
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// LP_TIMER_SEL_8M -> 0
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// LP_TIMER_SEL_RTC_SLOW -> 0
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
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/* Select slow clock source for BT momdule */
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switch (slow_clk_src) {
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case BT_SLOW_CLK_SRC_MAIN_XTAL:
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ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
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#ifdef CONFIG_XTAL_FREQ_26
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// LP_TIMER_CLK_DIV_NUM -> 130
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
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#else
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// LP_TIMER_CLK_DIV_NUM -> 250
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
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#endif // CONFIG_XTAL_FREQ_26
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// MODEM_CLKRST_ETM_CLK_ACTIVE -> 1
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// MODEM_CLKRST_ETM_CLK_SEL -> 0
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break;
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case BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0:
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ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 0, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
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break;
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default:
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ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported slow clock");
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assert(0);
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break;
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}
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SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 1, MODEM_CLKRST_ETM_CLK_ACTIVE_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
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}
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static ble_rtc_slow_clk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
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{
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ble_rtc_slow_clk_src_t slow_clk_src;
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#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
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#ifdef CONFIG_XTAL_FREQ_26
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cfg->rtc_freq = 40000;
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#else
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cfg->rtc_freq = 32000;
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#endif // CONFIG_XTAL_FREQ_26
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slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
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#else
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if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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cfg->rtc_freq = 32768;
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slow_clk_src = BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0;
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} else {
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ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
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#ifdef CONFIG_XTAL_FREQ_26
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cfg->rtc_freq = 40000;
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#else
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cfg->rtc_freq = 32000;
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#endif // CONFIG_XTAL_FREQ_26
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slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
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}
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#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
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esp_bt_rtc_slow_clk_select(slow_clk_src);
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return slow_clk_src;
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}
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esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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{
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esp_err_t ret = ESP_OK;
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ble_npl_count_info_t npl_info;
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ble_rtc_slow_clk_src_t rtc_clk_src;
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memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
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if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
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ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
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@ -588,7 +636,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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return ESP_ERR_INVALID_ARG;
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}
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ble_rtc_clk_init();
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rtc_clk_src = ble_rtc_clk_init(cfg);
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ret = esp_register_ext_funcs(&ext_funcs_ro);
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if (ret != ESP_OK) {
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@ -644,7 +692,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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#if CONFIG_SW_COEXIST_ENABLE
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coex_init();
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#endif
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ret = ble_controller_init(cfg);
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if (ret != ESP_OK) {
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ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
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@ -675,7 +722,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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}
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#endif // CONFIG_BT_CONTROLLER_LOG_ENABLED
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ret = controller_sleep_init();
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ret = controller_sleep_init(rtc_clk_src);
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if (ret != ESP_OK) {
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ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret);
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goto free_controller;
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -20,7 +20,9 @@ This example contains some build configurations. For each configuration, a few c
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- `sdkconfig.40m.esp32s3`: ESP32S3 uses main XTAL as low power clock in light sleep enabled.
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- `sdkconfig.defaults.esp32h2`: ESP32H2 uses 32kHz XTAL as low power clock in light sleep enabled.
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- `sdkconfig.32m.esp32h2`: ESP32H2 uses main XTAL as low power clock in light sleep enabled.
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- `sdkconfig.defaults.esp32c2`: ESP32C2 uses main XTAL as low power clock in light sleep enabled.
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- `sdkconfig.defaults.esp32c2`: ESP32C2 uses 32kHz XTAL as low power clock in light sleep enabled.
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- `sdkconfig.26m.esp32c2`: ESP32C2 uses main XTAL as low power clock in light sleep enabled.
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## How to use example
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### Hardware Required
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@ -39,9 +41,10 @@ idf.py menuconfig
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- `Component config > Power Management > [*] Support for power management`
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3. Configure FreeRTOS:
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- `Component config > FreeRTOS > Kernel`
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- `(1000) configTICK_RATE_HZ`
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- `[*] configUSE_TICKLESS_IDLE`
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- `(3) configEXPECTED_IDLE_TIME_BEFORE_SLEEP`
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- `(1000) configTICK_RATE_HZ`
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- `[*] configUSE_TICKLESS_IDLE`
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- `(3) configEXPECTED_IDLE_TIME_BEFORE_SLEEP`
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#### For Chip ESP32/ESP32-C3/ESP32-S3
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4. Enable power down MAC and baseband:
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@ -55,28 +58,19 @@ idf.py menuconfig
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7. Enable power up main XTAL during light sleep:
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- `Component config > Bluetooth > Controller Options > MODEM SLEEP Options > [*] power up main XTAL during light sleep`
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#### For Chip ESP32-C6/ESP32-H2
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#### For Chip ESP32-C6/ESP32-H2/ESP32-C2
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4. Enable bluetooth modem sleep:
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- `Component config > Bluetooth > Controller Options`
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- `[*] Enable BLE sleep`
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5. Configure bluetooth low power clock:
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- `Component config > Bluetooth > Controller Options > BLE low power clock source`
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- Use RTC clock source as low power clock sourceduring light sleep:
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- Use RTC clock source as low power clock source during light sleep:
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- `(X) Use system RTC slow clock source`
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6. Power down flash during light sleep:
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- `Component config > Hardware Settings > Sleep Config`
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- `[*] Power down flash in light sleep when there is no SPIRAM`
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#### For Chip ESP32-C2
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4. Enable bluetooth modem sleep:
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- `Component config > Bluetooth > Controller Options`
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- `[*] Enable BLE sleep`
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5. Power down flash during light sleep:
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- `Component config > Hardware Settings > Sleep Config`
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- `[*] Power down flash in light sleep when there is no SPIRAM`
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### Build and Flash
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```
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@ -102,7 +96,7 @@ See the Getting Started Guide for full steps to configure and use ESP-IDF to bui
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## Example Output
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When you run this example, the prints the following at the very begining:
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When you run this example, the prints the following at the very beginning:
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```
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I (333) cpu_start: Starting scheduler.
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@ -131,17 +125,19 @@ I (463) NimBLE:
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## Typical current consumption with management enabled
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| | max current | modem sleep | light sleep (main XTAL) | light sleep (32KHz XTAL) |
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| ------------------------------------------- | ----------- | ----------- | ----------------------- | ------------------------ |
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| ESP32 | 231 mA | 14.1 mA | X | 1.9 mA |
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| ESP32C3 | 262 mA | 12 mA | 2.3 mA | 140 uA |
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| ESP32S3 | 240 mA | 17.9 mA | 3.3 mA | 230 uA |
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| ESP32C6 | 240 mA | 22 mA | 3.3 mA | 34 uA |
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| ESP32H2 | 82 mA | 16.0 mA | 4.0 mA | 24 uA |
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| ESP32C2 | 130 mA | 18.0 mA | 2.5 mA | X |
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| | max current | modem sleep | light sleep (main XTAL) | light sleep (32KHz XTAL) |
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| ------- | ----------- | ----------- | ----------------------- | ------------------------ |
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| ESP32 | 231 mA | 14.1 mA | X | 1.9 mA |
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| ESP32C3 | 262 mA | 12 mA | 2.3 mA | 140 uA |
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| ESP32S3 | 240 mA | 17.9 mA | 3.3 mA | 230 uA |
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| ESP32C6 | 240 mA | 22 mA | 3.3 mA | 34 uA |
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| ESP32H2 | 82 mA | 16.0 mA | 4.0 mA | 24 uA |
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| ESP32C2 | 130 mA | 18.0 mA | 2.5 mA | 169 uA |
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X: This feature is currently not supported.
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## Example Breakdown
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- ESP32 does not support the use of main XTAL in light sleep mode, so an external 32kHz crystal is required.
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- ESP32C2 does not support the use of 32KHz XTAL in light sleep mode, the XTAL frequency is set to 26MHz in default.
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- ESP32C2 support XTAL frequency of 26MHz and 40MHz, the XTAL frequency is set to 26MHz in default.
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- ESP32C2 support external 32kHz crystal by connecting the crystal to the chip through pin0
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@ -0,0 +1,24 @@
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CONFIG_IDF_TARGET="esp32c2"
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# Bluetooth Low Power Config
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CONFIG_BT_LE_SLEEP_ENABLE=y
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CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL=y
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#
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# Power Management
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#
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CONFIG_PM_ENABLE=y
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CONFIG_PM_DFS_INIT_AUTO=y
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# XTAL Freq Config
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CONFIG_XTAL_FREQ_26=y
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CONFIG_XTAL_FREQ=26
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#
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# Sleep Config
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#
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CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
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CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
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# RTC clock source
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CONFIG_RTC_CLK_SRC_INT_RC=y
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@ -1,7 +1,8 @@
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CONFIG_IDF_TARGET="esp32h2"
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CONFIG_IDF_TARGET="esp32c2"
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# Bluetooth Low Power Config
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CONFIG_BT_LE_SLEEP_ENABLE=y
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CONFIG_BT_LE_LP_CLK_SRC_DEFAULT=y
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#
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# Power Management
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@ -18,3 +19,6 @@ CONFIG_XTAL_FREQ=26
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#
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CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
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CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
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# RTC clock source
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CONFIG_RTC_CLK_SRC_EXT_OSC=y
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||||
|
|
Ładowanie…
Reference in New Issue