From eb24a577284ea9cba615d850628e36a5d6772b4e Mon Sep 17 00:00:00 2001
From: Marius Vikhammer <marius.vikhammer@espressif.com>
Date: Wed, 12 Jun 2024 09:24:50 +0800
Subject: [PATCH] feat(intr): basic interrupt/freertos support for C61

---
 .../port/esp32c61/esp_cpu_intr.c              |  1 -
 .../esp32c61/include/hal/crosscore_int_ll.h   |  1 -
 components/idf_test/include/esp32c61/.gitkeep |  0
 .../include/esp32c61/idf_performance_target.h |  7 ++++
 components/riscv/interrupt.c                  | 41 -------------------
 5 files changed, 7 insertions(+), 43 deletions(-)
 delete mode 100644 components/idf_test/include/esp32c61/.gitkeep
 create mode 100644 components/idf_test/include/esp32c61/idf_performance_target.h

diff --git a/components/esp_hw_support/port/esp32c61/esp_cpu_intr.c b/components/esp_hw_support/port/esp32c61/esp_cpu_intr.c
index 129110fafc..ded3030aeb 100644
--- a/components/esp_hw_support/port/esp32c61/esp_cpu_intr.c
+++ b/components/esp_hw_support/port/esp32c61/esp_cpu_intr.c
@@ -7,7 +7,6 @@
 #include "esp_cpu.h"
 #include "esp_riscv_intr.h"
 
-//TODO: [ESP32C61] IDF-9262, inherit from C5
 void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
 {
     /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
diff --git a/components/hal/esp32c61/include/hal/crosscore_int_ll.h b/components/hal/esp32c61/include/hal/crosscore_int_ll.h
index 96f2e62336..c76790d756 100644
--- a/components/hal/esp32c61/include/hal/crosscore_int_ll.h
+++ b/components/hal/esp32c61/include/hal/crosscore_int_ll.h
@@ -12,7 +12,6 @@
 extern "C" {
 #endif
 
-// TODO: [ESP32C61] IDF-9262, inherit from ESP32C6
 
 /**
  * @brief Clear the crosscore interrupt that just occurred on the current core
diff --git a/components/idf_test/include/esp32c61/.gitkeep b/components/idf_test/include/esp32c61/.gitkeep
deleted file mode 100644
index e69de29bb2..0000000000
diff --git a/components/idf_test/include/esp32c61/idf_performance_target.h b/components/idf_test/include/esp32c61/idf_performance_target.h
new file mode 100644
index 0000000000..dd3f635e54
--- /dev/null
+++ b/components/idf_test/include/esp32c61/idf_performance_target.h
@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
diff --git a/components/riscv/interrupt.c b/components/riscv/interrupt.c
index 042929f266..ff5d40301c 100644
--- a/components/riscv/interrupt.c
+++ b/components/riscv/interrupt.c
@@ -14,29 +14,6 @@
 #include "riscv/rv_utils.h"
 
 
-// TODO: [ESP32C61] IDF-9261, added in verify code, pls check
-// #if SOC_INT_CLIC_SUPPORTED
-
-// /**
-//  * If the target is using the CLIC as the interrupt controller, we have 32 external interrupt lines and 16 internal
-//  * lines. Let's consider the internal ones reserved and not mappable to any handler.
-//  */
-// #define RV_EXTERNAL_INT_COUNT   32
-// #define RV_EXTERNAL_INT_OFFSET  (CLIC_EXT_INTR_NUM_OFFSET)
-
-// #else // !SOC_INT_CLIC_SUPPORTED
-
-// /**
-//  * In the case of INTC, all the interrupt lines are dedicated to external peripherals, so the offset is 0.
-//  * In the case of PLIC, the reserved interrupts are not contiguous, moreover, they are already marked as
-//  * unusable by the interrupt allocator, so the offset can also be 0 here.
-//  */
-// #define RV_EXTERNAL_INT_COUNT   32
-// #define RV_EXTERNAL_INT_OFFSET  0
-
-// #endif // SOC_INT_CLIC_SUPPORTED
-
-
 typedef struct {
     intr_handler_t handler;
     void *arg;
@@ -91,24 +68,6 @@ void _global_interrupt_handler(intptr_t sp, int mcause)
     }
 }
 
-// TODO: [ESP32C61] IDF-9261, added in verify code, pls check
-// /*************************** ESP-RV Interrupt Controller ***************************/
-
-// #if SOC_INT_CLIC_SUPPORTED
-
-// bool esprv_intc_int_is_vectored(int rv_int_num)
-// {
-//     const uint32_t shv = REG_GET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + RV_EXTERNAL_INT_OFFSET), CLIC_INT_ATTR_SHV);
-//     return shv != 0;
-// }
-
-// void esprv_intc_int_set_vectored(int rv_int_num, bool vectored)
-// {
-//     REG_SET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + RV_EXTERNAL_INT_OFFSET), CLIC_INT_ATTR_SHV, vectored ? 1 : 0);
-// }
-
-// #endif // SOC_INT_CLIC_SUPPORTED
-
 /*************************** Exception names. Used in .gdbinit file. ***************************/
 
 const char *riscv_excp_names[16] __attribute__((used)) = {