kopia lustrzana https://github.com/espressif/esp-idf
mspi: add octal psram get_cs_io function
rodzic
9b53e18c44
commit
ea10dacf68
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@ -38,7 +38,7 @@
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#define OCT_PSRAM_ADDR_BITLEN 32
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#define OCT_PSRAM_ADDR_BITLEN 32
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#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
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#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
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#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
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#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
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#define OCT_PSRAM_CS1_IO 26
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#define OCT_PSRAM_CS1_IO CONFIG_DEFAULT_PSRAM_CS_IO
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#define OCT_PSRAM_CS_SETUP_TIME 3
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#define OCT_PSRAM_CS_SETUP_TIME 3
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#define OCT_PSRAM_CS_HOLD_TIME 3
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#define OCT_PSRAM_CS_HOLD_TIME 3
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@ -102,6 +102,11 @@ static const char* TAG = "opi psram";
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static DRAM_ATTR psram_size_t s_psram_size;
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static DRAM_ATTR psram_size_t s_psram_size;
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static void IRAM_ATTR s_config_psram_spi_phases(void);
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static void IRAM_ATTR s_config_psram_spi_phases(void);
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uint8_t IRAM_ATTR psram_get_cs_io(void)
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{
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return OCT_PSRAM_CS1_IO;
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}
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/**
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/**
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* Initialise mode registers of the PSRAM
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* Initialise mode registers of the PSRAM
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*/
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*/
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@ -224,7 +229,7 @@ static void IRAM_ATTR s_init_psram_pins(void)
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//Set cs1 pin function
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//Set cs1 pin function
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[OCT_PSRAM_CS1_IO], FUNC_SPICS1_SPICS1);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[OCT_PSRAM_CS1_IO], FUNC_SPICS1_SPICS1);
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//Set mspi cs1 drive strength
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//Set mspi cs1 drive strength
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PIN_SET_DRV(IO_MUX_GPIO26_REG, 3);
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PIN_SET_DRV(GPIO_PIN_MUX_REG[OCT_PSRAM_CS1_IO], 3);
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//Set psram clock pin drive strength
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//Set psram clock pin drive strength
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REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3);
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REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3);
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}
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}
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