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Merge branch 'feature/s3_base_support' into 'master' 

soc: S3 base support

See merge request espressif/esp-idf!13827
pull/6904/head
Michael (XIAO Xufeng) 2021-06-07 12:07:08 +00:00
rodzic 731f16fc6a 19a492bc8d
commit e005ec0899
19 zmienionych plików z 4276 dodań i 3887 usunięć
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15
Kconfig
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@ -45,19 +45,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
default "y" if IDF_TARGET="esp32s3"
select IDF_TARGET_ARCH_XTENSA
choice IDF_TARGET_ESP32S3_BETA_VERSION
prompt "ESP32-S3 beta version"
depends on IDF_TARGET_ESP32S3
default IDF_TARGET_ESP32S3_BETA_VERSION_3
help
Currently ESP32-S3 has several beta versions for internal use only.
Select the one that matches your chip model.
config IDF_TARGET_ESP32S3_BETA_VERSION_3
bool
prompt "ESP32-S3 beta3"
endchoice
config IDF_TARGET_ESP32C3
bool
default "y" if IDF_TARGET="esp32c3"
@ -73,7 +60,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
default 0x0000 if IDF_TARGET_ESP32
default 0x0002 if IDF_TARGET_ESP32S2
default 0x0005 if IDF_TARGET_ESP32C3
default 0x0006 if IDF_TARGET_ESP32S3
default 0x0009 if IDF_TARGET_ESP32S3
default 0xFFFF
menu "SDK tool configuration"

2
components/bootloader_support/include/esp_app_format.h
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@ -15,7 +15,7 @@ typedef enum {
ESP_CHIP_ID_ESP32 = 0x0000, /*!< chip ID: ESP32 */
ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */
ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
ESP_CHIP_ID_ESP32S3 = 0x0006, /*!< chip ID: ESP32-S3 */
ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
} __attribute__((packed)) esp_chip_id_t;

3
components/esp_hw_support/port/esp32s3/rtc_init.c
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@ -86,9 +86,6 @@ void rtc_init(rtc_config_t cfg)
} else {
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
}
// CLEAR APLL close
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
//open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);

8
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
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@ -30,11 +30,9 @@ PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB );
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
/* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */
/* so here we directly assign the symbols with the ROM API address */
PROVIDE ( esp_rom_md5_init = 0x40001ac4 );
PROVIDE ( esp_rom_md5_update = 0x40001ad0 );
PROVIDE ( esp_rom_md5_final = 0x40001adc );
PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );

3890
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
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Plik diff jest za duży Load Diff

182
components/esp_rom/esp32s3/ld/esp32s3.rom.libgcc.ld
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@ -1,7 +1,7 @@
/* ROM function interface esp32s3.rom.libgcc.ld for esp32s3
*
*
* Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470
* Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,93 +13,93 @@
***************************************/
/* Functions */
__absvdi2 = 0x40001fd4;
__absvsi2 = 0x40001fe0;
__adddf3 = 0x40001fec;
__addsf3 = 0x40001ff8;
__addvdi3 = 0x40002004;
__addvsi3 = 0x40002010;
__ashldi3 = 0x4000201c;
__ashrdi3 = 0x40002028;
__bswapdi2 = 0x40002034;
__bswapsi2 = 0x40002040;
__clear_cache = 0x4000204c;
__clrsbdi2 = 0x40002058;
__clrsbsi2 = 0x40002064;
__clzdi2 = 0x40002070;
__clzsi2 = 0x4000207c;
__cmpdi2 = 0x40002088;
__ctzdi2 = 0x40002094;
__ctzsi2 = 0x400020a0;
__divdc3 = 0x400020ac;
__divdf3 = 0x400020b8;
__divdi3 = 0x400020c4;
__divsc3 = 0x400020d0;
__divsf3 = 0x400020dc;
__divsi3 = 0x400020e8;
__eqdf2 = 0x400020f4;
__eqsf2 = 0x40002100;
__extendsfdf2 = 0x4000210c;
__ffsdi2 = 0x40002118;
__ffssi2 = 0x40002124;
__fixdfdi = 0x40002130;
__fixdfsi = 0x4000213c;
__fixsfdi = 0x40002148;
__fixsfsi = 0x40002154;
__fixunsdfsi = 0x40002160;
__fixunssfdi = 0x4000216c;
__fixunssfsi = 0x40002178;
__floatdidf = 0x40002184;
__floatdisf = 0x40002190;
__floatsidf = 0x4000219c;
__floatsisf = 0x400021a8;
__floatundidf = 0x400021b4;
__floatundisf = 0x400021c0;
__floatunsidf = 0x400021cc;
__floatunsisf = 0x400021d8;
__gcc_bcmp = 0x400021e4;
__gedf2 = 0x400021f0;
__gesf2 = 0x400021fc;
__gtdf2 = 0x40002208;
__gtsf2 = 0x40002214;
__ledf2 = 0x40002220;
__lesf2 = 0x4000222c;
__lshrdi3 = 0x40002238;
__ltdf2 = 0x40002244;
__ltsf2 = 0x40002250;
__moddi3 = 0x4000225c;
__modsi3 = 0x40002268;
__muldc3 = 0x40002274;
__muldf3 = 0x40002280;
__muldi3 = 0x4000228c;
__mulsc3 = 0x40002298;
__mulsf3 = 0x400022a4;
__mulsi3 = 0x400022b0;
__mulvdi3 = 0x400022bc;
__mulvsi3 = 0x400022c8;
__nedf2 = 0x400022d4;
__negdf2 = 0x400022e0;
__negdi2 = 0x400022ec;
__negsf2 = 0x400022f8;
__negvdi2 = 0x40002304;
__negvsi2 = 0x40002310;
__nesf2 = 0x4000231c;
__paritysi2 = 0x40002328;
__popcountdi2 = 0x40002334;
__popcountsi2 = 0x40002340;
__powidf2 = 0x4000234c;
__powisf2 = 0x40002358;
__subdf3 = 0x40002364;
__subsf3 = 0x40002370;
__subvdi3 = 0x4000237c;
__subvsi3 = 0x40002388;
__truncdfsf2 = 0x40002394;
__ucmpdi2 = 0x400023a0;
__udivdi3 = 0x400023ac;
__udivmoddi4 = 0x400023b8;
__udivsi3 = 0x400023c4;
__udiv_w_sdiv = 0x400023d0;
__umoddi3 = 0x400023dc;
__umodsi3 = 0x400023e8;
__unorddf2 = 0x400023f4;
__unordsf2 = 0x40002400;
__absvdi2 = 0x4000216c;
__absvsi2 = 0x40002178;
__adddf3 = 0x40002184;
__addsf3 = 0x40002190;
__addvdi3 = 0x4000219c;
__addvsi3 = 0x400021a8;
__ashldi3 = 0x400021b4;
__ashrdi3 = 0x400021c0;
__bswapdi2 = 0x400021cc;
__bswapsi2 = 0x400021d8;
__clear_cache = 0x400021e4;
__clrsbdi2 = 0x400021f0;
__clrsbsi2 = 0x400021fc;
__clzdi2 = 0x40002208;
__clzsi2 = 0x40002214;
__cmpdi2 = 0x40002220;
__ctzdi2 = 0x4000222c;
__ctzsi2 = 0x40002238;
__divdc3 = 0x40002244;
__divdf3 = 0x40002250;
__divdi3 = 0x4000225c;
__divsc3 = 0x40002268;
__divsf3 = 0x40002274;
__divsi3 = 0x40002280;
__eqdf2 = 0x4000228c;
__eqsf2 = 0x40002298;
__extendsfdf2 = 0x400022a4;
__ffsdi2 = 0x400022b0;
__ffssi2 = 0x400022bc;
__fixdfdi = 0x400022c8;
__fixdfsi = 0x400022d4;
__fixsfdi = 0x400022e0;
__fixsfsi = 0x400022ec;
__fixunsdfsi = 0x400022f8;
__fixunssfdi = 0x40002304;
__fixunssfsi = 0x40002310;
__floatdidf = 0x4000231c;
__floatdisf = 0x40002328;
__floatsidf = 0x40002334;
__floatsisf = 0x40002340;
__floatundidf = 0x4000234c;
__floatundisf = 0x40002358;
__floatunsidf = 0x40002364;
__floatunsisf = 0x40002370;
__gcc_bcmp = 0x4000237c;
__gedf2 = 0x40002388;
__gesf2 = 0x40002394;
__gtdf2 = 0x400023a0;
__gtsf2 = 0x400023ac;
__ledf2 = 0x400023b8;
__lesf2 = 0x400023c4;
__lshrdi3 = 0x400023d0;
__ltdf2 = 0x400023dc;
__ltsf2 = 0x400023e8;
__moddi3 = 0x400023f4;
__modsi3 = 0x40002400;
__muldc3 = 0x4000240c;
__muldf3 = 0x40002418;
__muldi3 = 0x40002424;
__mulsc3 = 0x40002430;
__mulsf3 = 0x4000243c;
__mulsi3 = 0x40002448;
__mulvdi3 = 0x40002454;
__mulvsi3 = 0x40002460;
__nedf2 = 0x4000246c;
__negdf2 = 0x40002478;
__negdi2 = 0x40002484;
__negsf2 = 0x40002490;
__negvdi2 = 0x4000249c;
__negvsi2 = 0x400024a8;
__nesf2 = 0x400024b4;
__paritysi2 = 0x400024c0;
__popcountdi2 = 0x400024cc;
__popcountsi2 = 0x400024d8;
__powidf2 = 0x400024e4;
__powisf2 = 0x400024f0;
__subdf3 = 0x400024fc;
__subsf3 = 0x40002508;
__subvdi3 = 0x40002514;
__subvsi3 = 0x40002520;
__truncdfsf2 = 0x4000252c;
__ucmpdi2 = 0x40002538;
__udivdi3 = 0x40002544;
__udivmoddi4 = 0x40002550;
__udivsi3 = 0x4000255c;
__udiv_w_sdiv = 0x40002568;
__umoddi3 = 0x40002574;
__umodsi3 = 0x40002580;
__unorddf2 = 0x4000258c;
__unordsf2 = 0x40002598;

26
components/esp_rom/esp32s3/ld/esp32s3.rom.newlib-nano.ld
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@ -1,7 +1,7 @@
/* ROM function interface esp32s3.rom.newlib-nano.ld for esp32s3
*
*
* Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470
* Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,15 +13,15 @@
***************************************/
/* Functions */
__sprint_r = 0x400013f8;
_fiprintf_r = 0x40001404;
_fprintf_r = 0x40001410;
_printf_common = 0x4000141c;
_printf_i = 0x40001428;
_vfiprintf_r = 0x40001434;
_vfprintf_r = 0x40001440;
fiprintf = 0x4000144c;
fprintf = 0x40001458;
printf = 0x40001464;
vfiprintf = 0x40001470;
vfprintf = 0x4000147c;
__sprint_r = 0x4000156c;
_fiprintf_r = 0x40001578;
_fprintf_r = 0x40001584;
_printf_common = 0x40001590;
_printf_i = 0x4000159c;
_vfiprintf_r = 0x400015a8;
_vfprintf_r = 0x400015b4;
fiprintf = 0x400015c0;
fprintf = 0x400015cc;
printf = 0x400015d8;
vfiprintf = 0x400015e4;
vfprintf = 0x400015f0;

158
components/esp_rom/esp32s3/ld/esp32s3.rom.newlib.ld
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@ -1,7 +1,7 @@
/* ROM function interface esp32s3.rom.newlib.ld for esp32s3
*
*
* Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470
* Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,82 +13,82 @@
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x40001068;
memset = 0x40001074;
memcpy = 0x40001080;
memmove = 0x4000108c;
memcmp = 0x40001098;
strcpy = 0x400010a4;
strncpy = 0x400010b0;
strcmp = 0x400010bc;
strncmp = 0x400010c8;
strlen = 0x400010d4;
strstr = 0x400010e0;
bzero = 0x400010ec;
_isatty_r = 0x400010f8;
sbrk = 0x40001104;
isalnum = 0x40001110;
isalpha = 0x4000111c;
isascii = 0x40001128;
isblank = 0x40001134;
iscntrl = 0x40001140;
isdigit = 0x4000114c;
islower = 0x40001158;
isgraph = 0x40001164;
isprint = 0x40001170;
ispunct = 0x4000117c;
isspace = 0x40001188;
isupper = 0x40001194;
toupper = 0x400011a0;
tolower = 0x400011ac;
toascii = 0x400011b8;
memccpy = 0x400011c4;
memchr = 0x400011d0;
memrchr = 0x400011dc;
strcasecmp = 0x400011e8;
strcasestr = 0x400011f4;
strcat = 0x40001200;
strdup = 0x4000120c;
strchr = 0x40001218;
strcspn = 0x40001224;
strcoll = 0x40001230;
strlcat = 0x4000123c;
strlcpy = 0x40001248;
strlwr = 0x40001254;
strncasecmp = 0x40001260;
strncat = 0x4000126c;
strndup = 0x40001278;
strnlen = 0x40001284;
strrchr = 0x40001290;
strsep = 0x4000129c;
strspn = 0x400012a8;
strtok_r = 0x400012b4;
strupr = 0x400012c0;
longjmp = 0x400012cc;
setjmp = 0x400012d8;
abs = 0x400012e4;
div = 0x400012f0;
labs = 0x400012fc;
ldiv = 0x40001308;
qsort = 0x40001314;
rand_r = 0x40001320;
rand = 0x4000132c;
srand = 0x40001338;
utoa = 0x40001344;
itoa = 0x40001350;
atoi = 0x4000135c;
atol = 0x40001368;
strtol = 0x40001374;
strtoul = 0x40001380;
PROVIDE( fflush = 0x4000138c );
PROVIDE( _fflush_r = 0x40001398 );
PROVIDE( _fwalk = 0x400013a4 );
PROVIDE( _fwalk_reent = 0x400013b0 );
PROVIDE( __smakebuf_r = 0x400013bc );
PROVIDE( __swhatbuf_r = 0x400013c8 );
PROVIDE( __swbuf_r = 0x400013d4 );
__swbuf = 0x400013e0;
PROVIDE( __swsetup_r = 0x400013ec );
esp_rom_newlib_init_common_mutexes = 0x400011dc;
memset = 0x400011e8;
memcpy = 0x400011f4;
memmove = 0x40001200;
memcmp = 0x4000120c;
strcpy = 0x40001218;
strncpy = 0x40001224;
strcmp = 0x40001230;
strncmp = 0x4000123c;
strlen = 0x40001248;
strstr = 0x40001254;
bzero = 0x40001260;
_isatty_r = 0x4000126c;
sbrk = 0x40001278;
isalnum = 0x40001284;
isalpha = 0x40001290;
isascii = 0x4000129c;
isblank = 0x400012a8;
iscntrl = 0x400012b4;
isdigit = 0x400012c0;
islower = 0x400012cc;
isgraph = 0x400012d8;
isprint = 0x400012e4;
ispunct = 0x400012f0;
isspace = 0x400012fc;
isupper = 0x40001308;
toupper = 0x40001314;
tolower = 0x40001320;
toascii = 0x4000132c;
memccpy = 0x40001338;
memchr = 0x40001344;
memrchr = 0x40001350;
strcasecmp = 0x4000135c;
strcasestr = 0x40001368;
strcat = 0x40001374;
strdup = 0x40001380;
strchr = 0x4000138c;
strcspn = 0x40001398;
strcoll = 0x400013a4;
strlcat = 0x400013b0;
strlcpy = 0x400013bc;
strlwr = 0x400013c8;
strncasecmp = 0x400013d4;
strncat = 0x400013e0;
strndup = 0x400013ec;
strnlen = 0x400013f8;
strrchr = 0x40001404;
strsep = 0x40001410;
strspn = 0x4000141c;
strtok_r = 0x40001428;
strupr = 0x40001434;
longjmp = 0x40001440;
setjmp = 0x4000144c;
abs = 0x40001458;
div = 0x40001464;
labs = 0x40001470;
ldiv = 0x4000147c;
qsort = 0x40001488;
rand_r = 0x40001494;
rand = 0x400014a0;
srand = 0x400014ac;
utoa = 0x400014b8;
itoa = 0x400014c4;
atoi = 0x400014d0;
atol = 0x400014dc;
strtol = 0x400014e8;
strtoul = 0x400014f4;
PROVIDE( fflush = 0x40001500 );
PROVIDE( _fflush_r = 0x4000150c );
PROVIDE( _fwalk = 0x40001518 );
PROVIDE( _fwalk_reent = 0x40001524 );
PROVIDE( __smakebuf_r = 0x40001530 );
PROVIDE( __swhatbuf_r = 0x4000153c );
PROVIDE( __swbuf_r = 0x40001548 );
__swbuf = 0x40001554;
PROVIDE( __swsetup_r = 0x40001560 );
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fceffe0;
_global_impure_ptr = 0x3fceffdc;
syscall_table_ptr = 0x3fceffd4;
_global_impure_ptr = 0x3fceffd0;

6
components/esp_rom/patches/esp_rom_sys.c
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@ -18,12 +18,6 @@
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#endif
IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c))
{
extern void ets_install_putc1(void (*p)(char c));

2
components/esptool_py/esptool

@ -1 +1 @@
Subproject commit e5f94fa7ea60403e804d782115f440385e8a5edd
Subproject commit 1c9fe7059738ecd8e2b77c66cf7e2be73e566c16

5
components/esptool_py/project_include.cmake
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@ -6,11 +6,6 @@ idf_build_get_property(python PYTHON)
idf_build_get_property(idf_path IDF_PATH)
set(chip_model ${target})
if(target STREQUAL "esp32s3")
if(CONFIG_IDF_TARGET_ESP32S3_BETA_VERSION_3)
set(chip_model "esp32s3beta3")
endif()
endif()
set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model})
set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py")

136
components/hal/esp32s3/include/hal/gdma_ll.h
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@ -48,17 +48,21 @@ extern "C" {
#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
#define GDMA_LL_EVENT_RX_DONE (1<<0)
/* Memory block size value supported by TX channel */
#define GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B (0)
#define GDMA_LL_OUT_EXT_MEM_BK_SIZE_32B (1)
///////////////////////////////////// Common /////////////////////////////////////////
/**
* @brief Enable DMA channel M2M mode (TX channel n forward data to RX channel n), disabled by default
*/
static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in[channel].conf0.mem_trans_en = enable;
dev->channel[channel].in.conf0.mem_trans_en = enable;
if (enable) {
// to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value
dev->in[channel].peri_sel.sel = 0;
dev->out[channel].peri_sel.sel = 0;
dev->channel[channel].in.peri_sel.sel = 0;
dev->channel[channel].out.peri_sel.sel = 0;
}
}
@ -76,7 +80,7 @@ static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable)
*/
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
{
return dev->in[channel].int_st.val;
return dev->channel[channel].in.int_st.val;
}
/**
@ -85,9 +89,9 @@ static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t
static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->in[channel].int_ena.val |= mask;
dev->channel[channel].in.int_ena.val |= mask;
} else {
dev->in[channel].int_ena.val &= ~mask;
dev->channel[channel].in.int_ena.val &= ~mask;
}
}
@ -96,7 +100,7 @@ static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel
*/
static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->in[channel].int_clr.val = mask;
dev->channel[channel].in.int_clr.val = mask;
}
/**
@ -104,7 +108,7 @@ static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t c
*/
static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->in[channel].int_st);
return (volatile void *)(&dev->channel[channel].in.int_st);
}
/**
@ -112,7 +116,7 @@ static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev
*/
static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in[channel].conf1.in_check_owner = enable;
dev->channel[channel].in.conf1.in_check_owner = enable;
}
/**
@ -120,7 +124,7 @@ static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in[channel].conf0.in_data_burst_en = enable;
dev->channel[channel].in.conf0.in_data_burst_en = enable;
}
/**
@ -128,7 +132,7 @@ static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channe
*/
static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in[channel].conf0.indscr_burst_en = enable;
dev->channel[channel].in.conf0.indscr_burst_en = enable;
}
/**
@ -136,8 +140,8 @@ static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t
*/
static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
dev->in[channel].conf0.in_rst = 1;
dev->in[channel].conf0.in_rst = 0;
dev->channel[channel].in.conf0.in_rst = 1;
dev->channel[channel].in.conf0.in_rst = 0;
}
/**
@ -146,7 +150,7 @@ static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
{
dev->in[channel].conf1.in_ext_mem_bk_size = size_index;
dev->channel[channel].in.conf1.in_ext_mem_bk_size = size_index;
}
/**
@ -154,7 +158,7 @@ static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t cha
*/
static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel, uint32_t water_mark)
{
dev->in[channel].conf1.dma_infifo_full_thrs = water_mark;
dev->channel[channel].in.conf1.dma_infifo_full_thrs = water_mark;
}
/**
@ -163,7 +167,7 @@ static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel,
*/
static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->in[channel].infifo_status.val & (1 << 2 * (fifo_level - 1));
return dev->channel[channel].in.infifo_status.val & (1 << 2 * (fifo_level - 1));
}
/**
@ -172,7 +176,7 @@ static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->in[channel].infifo_status.val & (1 << (2 * (fifo_level - 1) + 1));
return dev->channel[channel].in.infifo_status.val & (1 << (2 * (fifo_level - 1) + 1));
}
/**
@ -183,11 +187,11 @@ static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
{
switch (fifo_level) {
case 1:
return dev->in[channel].infifo_status.infifo_cnt_l1;
return dev->channel[channel].in.infifo_status.infifo_cnt_l1;
case 2:
return dev->in[channel].infifo_status.infifo_cnt_l2;
return dev->channel[channel].in.infifo_status.infifo_cnt_l2;
case 3:
return dev->in[channel].infifo_status.infifo_cnt_l3;
return dev->channel[channel].in.infifo_status.infifo_cnt_l3;
}
}
@ -196,8 +200,8 @@ static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
*/
static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
{
dev->in[channel].pop.infifo_pop = 1;
return dev->in[channel].pop.infifo_rdata;
dev->channel[channel].in.pop.infifo_pop = 1;
return dev->channel[channel].in.pop.infifo_rdata;
}
/**
@ -205,7 +209,7 @@ static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
dev->in[channel].link.addr = addr;
dev->channel[channel].in.link.addr = addr;
}
/**
@ -213,7 +217,7 @@ static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, u
*/
static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
{
dev->in[channel].link.start = 1;
dev->channel[channel].in.link.start = 1;
}
/**
@ -221,7 +225,7 @@ static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
{
dev->in[channel].link.stop = 1;
dev->channel[channel].in.link.stop = 1;
}
/**
@ -229,7 +233,7 @@ static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
{
dev->in[channel].link.restart = 1;
dev->channel[channel].in.link.restart = 1;
}
/**
@ -237,7 +241,7 @@ static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in[channel].link.auto_ret = enable;
dev->channel[channel].in.link.auto_ret = enable;
}
/**
@ -245,7 +249,7 @@ static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t chann
*/
static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
return dev->in[channel].link.park;
return dev->channel[channel].in.link.park;
}
/**
@ -253,7 +257,7 @@ static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
*/
static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in[channel].suc_eof_des_addr;
return dev->channel[channel].in.suc_eof_des_addr;
}
/**
@ -261,7 +265,7 @@ static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uin
*/
static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in[channel].err_eof_des_addr;
return dev->channel[channel].in.err_eof_des_addr;
}
/**
@ -269,7 +273,7 @@ static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint3
*/
static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in[channel].dscr;
return dev->channel[channel].in.dscr;
}
/**
@ -277,7 +281,7 @@ static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_
*/
static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight)
{
dev->in[channel].wight.rx_weight = weight;
dev->channel[channel].in.wight.rx_weight = weight;
}
/**
@ -285,7 +289,7 @@ static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint
*/
static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->in[channel].pri.rx_pri = prio;
dev->channel[channel].in.pri.rx_pri = prio;
}
/**
@ -293,7 +297,7 @@ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->in[channel].peri_sel.sel = periph_id;
dev->channel[channel].in.peri_sel.sel = periph_id;
}
/**
@ -304,7 +308,7 @@ static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
{
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
dev->in[channel].sram_size.in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
dev->sram_size[channel].in.in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
}
}
@ -315,7 +319,7 @@ static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t c
*/
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
{
return dev->out[channel].int_st.val;
return dev->channel[channel].out.int_st.val;
}
/**
@ -324,9 +328,9 @@ static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t
static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->out[channel].int_ena.val |= mask;
dev->channel[channel].out.int_ena.val |= mask;
} else {
dev->out[channel].int_ena.val &= ~mask;
dev->channel[channel].out.int_ena.val &= ~mask;
}
}
@ -335,7 +339,7 @@ static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel
*/
static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->out[channel].int_clr.val = mask;
dev->channel[channel].out.int_clr.val = mask;
}
/**
@ -343,7 +347,7 @@ static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t c
*/
static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->out[channel].int_st);
return (volatile void *)(&dev->channel[channel].out.int_st);
}
/**
@ -351,7 +355,7 @@ static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev
*/
static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->out[channel].conf1.out_check_owner = enable;
dev->channel[channel].out.conf1.out_check_owner = enable;
}
/**
@ -359,7 +363,7 @@ static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->out[channel].conf0.out_data_burst_en = enable;
dev->channel[channel].out.conf0.out_data_burst_en = enable;
}
/**
@ -367,7 +371,7 @@ static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channe
*/
static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->out[channel].conf0.outdscr_burst_en = enable;
dev->channel[channel].out.conf0.outdscr_burst_en = enable;
}
/**
@ -375,7 +379,7 @@ static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t
*/
static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
{
dev->out[channel].conf0.out_eof_mode = mode;
dev->channel[channel].out.conf0.out_eof_mode = mode;
}
/**
@ -383,7 +387,7 @@ static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->out[channel].conf0.out_auto_wrback = enable;
dev->channel[channel].out.conf0.out_auto_wrback = enable;
}
/**
@ -391,8 +395,8 @@ static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t c
*/
static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
dev->out[channel].conf0.out_rst = 1;
dev->out[channel].conf0.out_rst = 0;
dev->channel[channel].out.conf0.out_rst = 1;
dev->channel[channel].out.conf0.out_rst = 0;
}
/**
@ -401,7 +405,7 @@ static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
{
dev->out[channel].conf1.out_ext_mem_bk_size = size_index;
dev->channel[channel].out.conf1.out_ext_mem_bk_size = size_index;
}
/**
@ -410,7 +414,7 @@ static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t cha
*/
static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->out[channel].outfifo_status.val & (1 << 2 * (fifo_level - 1));
return dev->channel[channel].out.outfifo_status.val & (1 << 2 * (fifo_level - 1));
}
/**
@ -419,7 +423,7 @@ static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->out[channel].outfifo_status.val & (1 << (2 * (fifo_level - 1) + 1));
return dev->channel[channel].out.outfifo_status.val & (1 << (2 * (fifo_level - 1) + 1));
}
/**
@ -430,11 +434,11 @@ static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
{
switch (fifo_level) {
case 1:
return dev->out[channel].outfifo_status.outfifo_cnt_l1;
return dev->channel[channel].out.outfifo_status.outfifo_cnt_l1;
case 2:
return dev->out[channel].outfifo_status.outfifo_cnt_l2;
return dev->channel[channel].out.outfifo_status.outfifo_cnt_l2;
case 3:
return dev->out[channel].outfifo_status.outfifo_cnt_l3;
return dev->channel[channel].out.outfifo_status.outfifo_cnt_l3;
}
}
@ -443,8 +447,8 @@ static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
{
dev->out[channel].push.outfifo_wdata = data;
dev->out[channel].push.outfifo_push = 1;
dev->channel[channel].out.push.outfifo_wdata = data;
dev->channel[channel].out.push.outfifo_push = 1;
}
/**
@ -452,7 +456,7 @@ static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint3
*/
static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
dev->out[channel].link.addr = addr;
dev->channel[channel].out.link.addr = addr;
}
/**
@ -460,7 +464,7 @@ static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, u
*/
static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
{
dev->out[channel].link.start = 1;
dev->channel[channel].out.link.start = 1;
}
/**
@ -468,7 +472,7 @@ static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
{
dev->out[channel].link.stop = 1;
dev->channel[channel].out.link.stop = 1;
}
/**
@ -476,7 +480,7 @@ static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
{
dev->out[channel].link.restart = 1;
dev->channel[channel].out.link.restart = 1;
}
/**
@ -484,7 +488,7 @@ static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
*/
static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
return dev->out[channel].link.park;
return dev->channel[channel].out.link.park;
}
/**
@ -492,7 +496,7 @@ static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
*/
static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->out[channel].eof_des_addr;
return dev->channel[channel].out.eof_des_addr;
}
/**
@ -500,7 +504,7 @@ static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t ch
*/
static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->out[channel].dscr;
return dev->channel[channel].out.dscr;
}
/**
@ -508,7 +512,7 @@ static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_
*/
static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight)
{
dev->out[channel].wight.tx_weight = weight;
dev->channel[channel].out.wight.tx_weight = weight;
}
/**
@ -516,7 +520,7 @@ static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint
*/
static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->out[channel].pri.tx_pri = prio;
dev->channel[channel].out.pri.tx_pri = prio;
}
/**
@ -524,7 +528,7 @@ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
{
dev->out[channel].peri_sel.sel = periph_id;
dev->channel[channel].out.peri_sel.sel = periph_id;
}
/**
@ -535,7 +539,7 @@ static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
static inline void gdma_ll_tx_extend_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
{
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
dev->out[channel].sram_size.out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
dev->sram_size[channel].out.out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
}
}

4
components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c
Wyświetl plik

@ -67,8 +67,8 @@ static void esp_crypto_shared_dma_init_extmem(void)
/* An L2 FIFO bigger than 40 bytes is need when accessing external ram */
gdma_ll_tx_extend_fifo_size_to(&GDMA, tx_ch_id, 40);
gdma_ll_rx_extend_l2_fifo_size_to(&GDMA, rx_ch_id, 40);
gdma_ll_tx_set_block_size_psram(&GDMA, tx_ch_id, GDMA_OUT_EXT_MEM_BK_SIZE_16B);
gdma_ll_rx_set_block_size_psram(&GDMA, rx_ch_id, GDMA_OUT_EXT_MEM_BK_SIZE_16B);
gdma_ll_tx_set_block_size_psram(&GDMA, tx_ch_id, GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B);
gdma_ll_rx_set_block_size_psram(&GDMA, rx_ch_id, GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B);
}
#endif //SOC_GDMA_SUPPORT_EXTMEM

60
components/soc/esp32s3/include/soc/gdma_reg.h
Wyświetl plik

@ -544,7 +544,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/
#define GDMA_INLINK_DSCR_BF1_CH0_S 0
#define GDMA_IN_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x3C)
/* GDMA_RX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_RX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Rx channel 0. .*/
#define GDMA_RX_WEIGHT_CH0 0x0000000F
#define GDMA_RX_WEIGHT_CH0_M ((GDMA_RX_WEIGHT_CH0_V)<<(GDMA_RX_WEIGHT_CH0_S))
@ -563,7 +563,7 @@ y..*/
#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x48)
/* GDMA_PERI_IN_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/
#define GDMA_PERI_IN_SEL_CH0 0x0000003F
#define GDMA_PERI_IN_SEL_CH0_M ((GDMA_PERI_IN_SEL_CH0_V)<<(GDMA_PERI_IN_SEL_CH0_S))
#define GDMA_PERI_IN_SEL_CH0_V 0x3F
@ -619,11 +619,6 @@ r has been transmitted..*/
#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V)<<(GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S))
#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V 0x3
#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S 13
/* Memory block size value supported by TX channel */
#define GDMA_OUT_EXT_MEM_BK_SIZE_16B (0)
#define GDMA_OUT_EXT_MEM_BK_SIZE_32B (1)
/* GDMA_OUT_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/
#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12))
@ -1032,7 +1027,7 @@ nk descriptor..*/
#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0
#define GDMA_OUT_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x9C)
/* GDMA_TX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_TX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Tx channel 0. .*/
#define GDMA_TX_WEIGHT_CH0 0x0000000F
#define GDMA_TX_WEIGHT_CH0_M ((GDMA_TX_WEIGHT_CH0_V)<<(GDMA_TX_WEIGHT_CH0_S))
@ -1051,7 +1046,8 @@ y..*/
#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xA8)
/* GDMA_PERI_OUT_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE
S. 8: SHA. 9: ADC_DAC..*/
#define GDMA_PERI_OUT_SEL_CH0 0x0000003F
#define GDMA_PERI_OUT_SEL_CH0_M ((GDMA_PERI_OUT_SEL_CH0_V)<<(GDMA_PERI_OUT_SEL_CH0_S))
#define GDMA_PERI_OUT_SEL_CH0_V 0x3F
@ -1100,11 +1096,6 @@ scriptor when accessing internal SRAM. .*/
#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH1_V)<<(GDMA_IN_EXT_MEM_BK_SIZE_CH1_S))
#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_V 0x3
#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_S 13
/* Memory block size value supported by RX channel */
#define GDMA_IN_EXT_MEM_BK_SIZE_16B (0)
#define GDMA_IN_EXT_MEM_BK_SIZE_32B (1)
/* GDMA_IN_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/
#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12))
@ -1586,7 +1577,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/
#define GDMA_INLINK_DSCR_BF1_CH1_S 0
#define GDMA_IN_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0xFC)
/* GDMA_RX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_RX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Rx channel 1. .*/
#define GDMA_RX_WEIGHT_CH1 0x0000000F
#define GDMA_RX_WEIGHT_CH1_M ((GDMA_RX_WEIGHT_CH1_V)<<(GDMA_RX_WEIGHT_CH1_S))
@ -1605,7 +1596,7 @@ y..*/
#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x108)
/* GDMA_PERI_IN_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/
#define GDMA_PERI_IN_SEL_CH1 0x0000003F
#define GDMA_PERI_IN_SEL_CH1_M ((GDMA_PERI_IN_SEL_CH1_V)<<(GDMA_PERI_IN_SEL_CH1_S))
#define GDMA_PERI_IN_SEL_CH1_V 0x3F
@ -2069,7 +2060,7 @@ nk descriptor..*/
#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0
#define GDMA_OUT_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x15C)
/* GDMA_TX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_TX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Tx channel 1. .*/
#define GDMA_TX_WEIGHT_CH1 0x0000000F
#define GDMA_TX_WEIGHT_CH1_M ((GDMA_TX_WEIGHT_CH1_V)<<(GDMA_TX_WEIGHT_CH1_S))
@ -2088,7 +2079,8 @@ y..*/
#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x168)
/* GDMA_PERI_OUT_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE
S. 8: SHA. 9: ADC_DAC..*/
#define GDMA_PERI_OUT_SEL_CH1 0x0000003F
#define GDMA_PERI_OUT_SEL_CH1_M ((GDMA_PERI_OUT_SEL_CH1_V)<<(GDMA_PERI_OUT_SEL_CH1_S))
#define GDMA_PERI_OUT_SEL_CH1_V 0x3F
@ -2618,7 +2610,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/
#define GDMA_INLINK_DSCR_BF1_CH2_S 0
#define GDMA_IN_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x1BC)
/* GDMA_RX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_RX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Rx channel 2. .*/
#define GDMA_RX_WEIGHT_CH2 0x0000000F
#define GDMA_RX_WEIGHT_CH2_M ((GDMA_RX_WEIGHT_CH2_V)<<(GDMA_RX_WEIGHT_CH2_S))
@ -2637,7 +2629,7 @@ y..*/
#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x1C8)
/* GDMA_PERI_IN_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/
#define GDMA_PERI_IN_SEL_CH2 0x0000003F
#define GDMA_PERI_IN_SEL_CH2_M ((GDMA_PERI_IN_SEL_CH2_V)<<(GDMA_PERI_IN_SEL_CH2_S))
#define GDMA_PERI_IN_SEL_CH2_V 0x3F
@ -3101,7 +3093,7 @@ nk descriptor..*/
#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0
#define GDMA_OUT_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x21C)
/* GDMA_TX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_TX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Tx channel 2. .*/
#define GDMA_TX_WEIGHT_CH2 0x0000000F
#define GDMA_TX_WEIGHT_CH2_M ((GDMA_TX_WEIGHT_CH2_V)<<(GDMA_TX_WEIGHT_CH2_S))
@ -3120,7 +3112,8 @@ y..*/
#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x228)
/* GDMA_PERI_OUT_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE
S. 8: SHA. 9: ADC_DAC..*/
#define GDMA_PERI_OUT_SEL_CH2 0x0000003F
#define GDMA_PERI_OUT_SEL_CH2_M ((GDMA_PERI_OUT_SEL_CH2_V)<<(GDMA_PERI_OUT_SEL_CH2_S))
#define GDMA_PERI_OUT_SEL_CH2_V 0x3F
@ -3650,7 +3643,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/
#define GDMA_INLINK_DSCR_BF1_CH3_S 0
#define GDMA_IN_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x27C)
/* GDMA_RX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_RX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Rx channel 3. .*/
#define GDMA_RX_WEIGHT_CH3 0x0000000F
#define GDMA_RX_WEIGHT_CH3_M ((GDMA_RX_WEIGHT_CH3_V)<<(GDMA_RX_WEIGHT_CH3_S))
@ -3669,7 +3662,7 @@ y..*/
#define GDMA_IN_PERI_SEL_CH3_REG (DR_REG_GDMA_BASE + 0x288)
/* GDMA_PERI_IN_SEL_CH3 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Rx channel 3. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/
#define GDMA_PERI_IN_SEL_CH3 0x0000003F
#define GDMA_PERI_IN_SEL_CH3_M ((GDMA_PERI_IN_SEL_CH3_V)<<(GDMA_PERI_IN_SEL_CH3_S))
#define GDMA_PERI_IN_SEL_CH3_V 0x3F
@ -4133,7 +4126,7 @@ nk descriptor..*/
#define GDMA_OUTLINK_DSCR_BF1_CH3_S 0
#define GDMA_OUT_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x2DC)
/* GDMA_TX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_TX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Tx channel 3. .*/
#define GDMA_TX_WEIGHT_CH3 0x0000000F
#define GDMA_TX_WEIGHT_CH3_M ((GDMA_TX_WEIGHT_CH3_V)<<(GDMA_TX_WEIGHT_CH3_S))
@ -4152,7 +4145,8 @@ y..*/
#define GDMA_OUT_PERI_SEL_CH3_REG (DR_REG_GDMA_BASE + 0x2E8)
/* GDMA_PERI_OUT_SEL_CH3 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Tx channel 3. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE
S. 8: SHA. 9: ADC_DAC..*/
#define GDMA_PERI_OUT_SEL_CH3 0x0000003F
#define GDMA_PERI_OUT_SEL_CH3_M ((GDMA_PERI_OUT_SEL_CH3_V)<<(GDMA_PERI_OUT_SEL_CH3_S))
#define GDMA_PERI_OUT_SEL_CH3_V 0x3F
@ -4682,7 +4676,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/
#define GDMA_INLINK_DSCR_BF1_CH4_S 0
#define GDMA_IN_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x33C)
/* GDMA_RX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_RX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Rx channel 4. .*/
#define GDMA_RX_WEIGHT_CH4 0x0000000F
#define GDMA_RX_WEIGHT_CH4_M ((GDMA_RX_WEIGHT_CH4_V)<<(GDMA_RX_WEIGHT_CH4_S))
@ -4701,7 +4695,7 @@ y..*/
#define GDMA_IN_PERI_SEL_CH4_REG (DR_REG_GDMA_BASE + 0x348)
/* GDMA_PERI_IN_SEL_CH4 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Rx channel 5. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/
#define GDMA_PERI_IN_SEL_CH4 0x0000003F
#define GDMA_PERI_IN_SEL_CH4_M ((GDMA_PERI_IN_SEL_CH4_V)<<(GDMA_PERI_IN_SEL_CH4_S))
#define GDMA_PERI_IN_SEL_CH4_V 0x3F
@ -5165,7 +5159,7 @@ nk descriptor..*/
#define GDMA_OUTLINK_DSCR_BF1_CH4_S 0
#define GDMA_OUT_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x39C)
/* GDMA_TX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/* GDMA_TX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'hf ; */
/*description: The weight of Tx channel 4. .*/
#define GDMA_TX_WEIGHT_CH4 0x0000000F
#define GDMA_TX_WEIGHT_CH4_M ((GDMA_TX_WEIGHT_CH4_V)<<(GDMA_TX_WEIGHT_CH4_S))
@ -5184,7 +5178,8 @@ y..*/
#define GDMA_OUT_PERI_SEL_CH4_REG (DR_REG_GDMA_BASE + 0x3A8)
/* GDMA_PERI_OUT_SEL_CH4 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: This register is used to select peripheral for Tx channel 4. 0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE
S. 8: SHA. 9: ADC_DAC..*/
#define GDMA_PERI_OUT_SEL_CH4 0x0000003F
#define GDMA_PERI_OUT_SEL_CH4_M ((GDMA_PERI_OUT_SEL_CH4_V)<<(GDMA_PERI_OUT_SEL_CH4_S))
#define GDMA_PERI_OUT_SEL_CH4_V 0x3F
@ -5374,7 +5369,8 @@ ing external RAM..*/
#define GDMA_EXTMEM_REJECT_CHANNEL_NUM_V 0xF
#define GDMA_EXTMEM_REJECT_CHANNEL_NUM_S 2
/* GDMA_EXTMEM_REJECT_ATTR : RO ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: The reject operation. Bit 0 is 1 indicate write data.*/
/*description: The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. B
it 1: if this bit is 1, the rejected accessing is WRITE..*/
#define GDMA_EXTMEM_REJECT_ATTR 0x00000003
#define GDMA_EXTMEM_REJECT_ATTR_M ((GDMA_EXTMEM_REJECT_ATTR_V)<<(GDMA_EXTMEM_REJECT_ATTR_S))
#define GDMA_EXTMEM_REJECT_ATTR_V 0x3
@ -5414,7 +5410,7 @@ d by permission control..*/
#define GDMA_EXTMEM_REJECT_INT_CLR_S 0
#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x40C)
/* GDMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101080 ; */
/* GDMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101180 ; */
/*description: register version..*/
#define GDMA_DATE 0xFFFFFFFF
#define GDMA_DATE_M ((GDMA_DATE_V)<<(GDMA_DATE_S))

733
components/soc/esp32s3/include/soc/gdma_struct.h
Wyświetl plik

@ -11,353 +11,347 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#ifndef _SOC_GDMA_STRUCT_H_
#define _SOC_GDMA_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
struct {
union {
struct {
uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
uint32_t in_loop_test : 1; /*reserved*/
uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */
uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t dma_infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/
uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/
uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. */
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t dma_infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/
uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/
uint32_t in_remain_under_1b_l3 : 1; /*reserved*/
uint32_t in_remain_under_2b_l3 : 1; /*reserved*/
uint32_t in_remain_under_3b_l3 : 1; /*reserved*/
uint32_t in_remain_under_4b_l3 : 1; /*reserved*/
uint32_t in_buf_hungry : 1; /*reserved*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} infifo_status;
union {
struct {
uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} pop;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/
uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25 : 7;
};
uint32_t val;
} link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/
uint32_t in_dscr_state : 2; /*reserved*/
uint32_t in_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} state;
uint32_t suc_eof_des_addr;
uint32_t err_eof_des_addr;
uint32_t dscr;
uint32_t dscr_bf0;
uint32_t dscr_bf1;
union {
struct {
uint32_t rx_weight : 4; /*The weight of Rx channel 0. */
uint32_t reserved4 : 28;
};
uint32_t val;
} wight;
union {
struct {
uint32_t in_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved5 : 27;
};
uint32_t val;
} sram_size;
union {
struct {
uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} peri_sel;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
} in[5];
struct {
union {
struct {
uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
uint32_t out_loop_test : 1; /*reserved*/
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */
uint32_t reserved6 : 26;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t reserved0 : 12;
uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */
uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */
uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. */
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/
uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/
uint32_t out_remain_under_1b_l3 : 1; /*reserved*/
uint32_t out_remain_under_2b_l3 : 1; /*reserved*/
uint32_t out_remain_under_3b_l3 : 1; /*reserved*/
uint32_t out_remain_under_4b_l3 : 1; /*reserved*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} outfifo_status;
union {
struct {
uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/
uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} push;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/
uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address. */
uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/
uint32_t reserved24 : 8;
};
uint32_t val;
} link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/
uint32_t out_dscr_state : 2; /*reserved*/
uint32_t out_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} state;
uint32_t eof_des_addr;
uint32_t eof_bfr_des_addr;
uint32_t dscr;
uint32_t dscr_bf0;
uint32_t dscr_bf1;
union {
struct {
uint32_t tx_weight : 4; /*The weight of Tx channel 0. */
uint32_t reserved4 : 28;
};
uint32_t val;
} wight;
union {
struct {
uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved5 : 27;
};
uint32_t val;
} sram_size;
union {
struct {
uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} peri_sel;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
} out[5];
struct {
union {
struct {
uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
uint32_t in_loop_test : 1; /*reserved*/
uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */
uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
uint32_t reserved5 : 1; /*reserved*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t dma_infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/
uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/
uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. */
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t dma_infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_cnt_l1 : 6; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/
uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/
uint32_t in_remain_under_1b_l3 : 1; /*reserved*/
uint32_t in_remain_under_2b_l3 : 1; /*reserved*/
uint32_t in_remain_under_3b_l3 : 1; /*reserved*/
uint32_t in_remain_under_4b_l3 : 1; /*reserved*/
uint32_t in_buf_hungry : 1; /*reserved*/
uint32_t reserved29 : 3; /*reserved*/
};
uint32_t val;
} infifo_status;
union {
struct {
uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} pop;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/
uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25 : 7;
};
uint32_t val;
} link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/
uint32_t in_dscr_state : 2; /*reserved*/
uint32_t in_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} state;
uint32_t suc_eof_des_addr;
uint32_t err_eof_des_addr;
uint32_t dscr;
uint32_t dscr_bf0;
uint32_t dscr_bf1;
union {
struct {
uint32_t reserved0 : 8;
uint32_t rx_weight : 4; /*The weight of Rx channel 0. */
uint32_t reserved12 : 20;
};
uint32_t val;
} wight;
uint32_t reserved_40;
union {
struct {
uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} peri_sel;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
} in;
struct {
union {
struct {
uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
uint32_t out_loop_test : 1; /*reserved*/
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */
uint32_t reserved6 : 1;
uint32_t reserved7 : 25;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t reserved0 : 12;
uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */
uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */
uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. */
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/
uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/
uint32_t out_remain_under_1b_l3 : 1; /*reserved*/
uint32_t out_remain_under_2b_l3 : 1; /*reserved*/
uint32_t out_remain_under_3b_l3 : 1; /*reserved*/
uint32_t out_remain_under_4b_l3 : 1; /*reserved*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} outfifo_status;
union {
struct {
uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/
uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} push;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/
uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address. */
uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/
uint32_t reserved24 : 8;
};
uint32_t val;
} link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/
uint32_t out_dscr_state : 2; /*reserved*/
uint32_t out_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} state;
uint32_t eof_des_addr;
uint32_t eof_bfr_des_addr;
uint32_t dscr;
uint32_t dscr_bf0;
uint32_t dscr_bf1;
union {
struct {
uint32_t reserved0 : 8;
uint32_t tx_weight : 4; /*The weight of Tx channel 0. */
uint32_t reserved12 : 20;
};
uint32_t val;
} wight;
uint32_t reserved_a0;
union {
struct {
uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AES. 8: SHA. 9: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} peri_sel;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
} out;
} channel[5];
union {
struct {
uint32_t ahb_testmode : 3; /*reserved*/
@ -382,14 +376,73 @@ typedef volatile struct {
uint32_t ahbm_rst_inter : 1; /*Set this bit, then clear this bit to reset the internal ahb FSM.*/
uint32_t ahbm_rst_exter : 1; /*Set this bit, then clear this bit to reset the external ahb FSM.*/
uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/
uint32_t reserved3 : 1;
uint32_t clk_en : 1;
uint32_t reserved4 : 28;
uint32_t reserved5 : 27;
};
uint32_t val;
} misc_conf;
struct {
union {
struct {
uint32_t in_size : 7; /*This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved7 : 25;
};
uint32_t val;
} in;
union {
struct {
uint32_t out_size : 7; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved7 : 25;
};
uint32_t val;
} out;
} sram_size[5];
uint32_t extmem_reject_addr;
union {
struct {
uint32_t extmem_reject_attr : 2; /*The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE.*/
uint32_t extmem_reject_channel_num : 4; /*The register indicate the reject accessing from which channel.*/
uint32_t extmem_reject_peri_num : 6; /*This register indicate reject accessing from which peripheral.*/
uint32_t reserved12 : 20;
};
uint32_t val;
} extmem_reject_st;
union {
struct {
uint32_t extmem_reject : 1; /*The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} extmem_reject_int_raw;
union {
struct {
uint32_t extmem_reject : 1; /*The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} extmem_reject_int_st;
union {
struct {
uint32_t extmem_reject : 1; /*The interrupt enable bit for the EXTMEM_REJECT_INT interrupt.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} extmem_reject_int_ena;
union {
struct {
uint32_t extmem_reject : 1; /*Set this bit to clear the EXTMEM_REJECT_INT interrupt.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} extmem_reject_int_clr;
uint32_t date;
} gdma_dev_t;
extern gdma_dev_t GDMA;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GDMA_STRUCT_H_ */

2610
components/soc/esp32s3/include/soc/rtc_cntl_reg.h
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168
components/soc/esp32s3/include/soc/rtc_cntl_struct.h
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@ -13,9 +13,12 @@
// limitations under the License.
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
union {
@ -149,8 +152,8 @@ typedef volatile struct {
uint32_t glitch_rst_en: 1;
uint32_t reserved21: 1; /*PLLA force power down*/
uint32_t sar_i2c_pu: 1; /*PLLA force power up*/
uint32_t plla_force_pd: 1; /*PLLA force power down*/
uint32_t plla_force_pu: 1; /*PLLA force power up*/
uint32_t analog_top_iso_sleep: 1; /*PLLA force power down*/
uint32_t analog_top_iso_monitor: 1; /*PLLA force power up*/
uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/
uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/
uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/
@ -358,24 +361,27 @@ typedef volatile struct {
} sdio_act_conf;
union {
struct {
uint32_t reserved0: 3;
uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/
uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/
uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/
uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/
uint32_t reserved11: 1;
uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/
uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/
uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/
uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/
uint32_t ck8m_force_pd: 1; /*CK8M force power down*/
uint32_t ck8m_force_pu: 1; /*CK8M force power up*/
uint32_t reserved27: 2;
uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/
uint32_t ana_clk_rtc_sel: 2;
uint32_t reserved0: 1;
uint32_t efuse_clk_force_gating: 1;
uint32_t efuse_clk_force_nogating: 1;
uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/
uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/
uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/
uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/
uint32_t reserved11: 1;
uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/
uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/
uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/
uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/
uint32_t ck8m_force_pd: 1; /*CK8M force power down*/
uint32_t ck8m_force_pu: 1; /*CK8M force power up*/
uint32_t xtal_global_force_gating: 1;
uint32_t xtal_global_force_nogating: 1;
uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/
uint32_t ana_clk_rtc_sel: 2;
};
uint32_t val;
} clk_conf;
@ -465,6 +471,16 @@ typedef volatile struct {
};
uint32_t val;
} rtc_pwc;
union {
struct {
uint32_t rtculator_drv_b_monitor : 6;
uint32_t rtculator_drv_b_slp : 6;
uint32_t dg_vdd_drv_b_slp : 8;
uint32_t dg_vdd_drv_b_monitor : 8;
uint32_t reserved28 : 4;
};
uint32_t val;
} regulator_drv_ctrl;
union {
struct {
uint32_t reserved0: 3;
@ -822,7 +838,9 @@ typedef volatile struct {
uint32_t usb_tx_en_override: 1;
uint32_t usb_reset_disable: 1;
uint32_t io_mux_reset_disable: 1;
uint32_t reserved19: 13;
uint32_t sw_usb_phy_sel: 1;
uint32_t sw_hw_usb_phy_sel: 1;
uint32_t reserved21: 11;
};
uint32_t val;
} usb_conf;
@ -918,26 +936,114 @@ typedef volatile struct {
} int_ena_w1tc;
union {
struct {
uint32_t reserved0: 18;
uint32_t retention_clk_sel: 1;
uint32_t retention_done_wait: 3;
uint32_t retention_clkoff_wait: 4;
uint32_t retention_en: 1;
uint32_t retention_wait: 5; /*wait cycles for rention operation*/
uint32_t reserved0 : 10;
uint32_t retention_tag_mode : 4;
uint32_t retention_target : 2;
uint32_t retention_clk_sel : 1;
uint32_t retention_done_wait : 3;
uint32_t retention_clkoff_wait : 4;
uint32_t retention_en : 1;
uint32_t retention_wait : 7; /*wait cycles for rention operation*/
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/
uint32_t reserved3: 29;
uint32_t reserved0 : 26;
uint32_t power_glitch_dsense : 2;
uint32_t power_glitch_force_pd : 1;
uint32_t power_glitch_force_pu : 1;
uint32_t power_glitch_efuse_sel : 1; /*select use analog fib signal*/
uint32_t power_glitch_en : 1;
};
uint32_t val;
} pg_ctrl;
union {
struct {
uint32_t rtc_fib_sel : 3;
uint32_t reserved3 : 29;
};
uint32_t val;
} fib_sel;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
uint32_t reserved0 : 2;
uint32_t touch_pad9_dac : 3;
uint32_t touch_pad8_dac : 3;
uint32_t touch_pad7_dac : 3;
uint32_t touch_pad6_dac : 3;
uint32_t touch_pad5_dac : 3;
uint32_t touch_pad4_dac : 3;
uint32_t touch_pad3_dac : 3;
uint32_t touch_pad2_dac : 3;
uint32_t touch_pad1_dac : 3;
uint32_t touch_pad0_dac : 3;
};
uint32_t val;
} touch_dac;
union {
struct {
uint32_t reserved0 : 17;
uint32_t touch_pad14_dac : 3;
uint32_t touch_pad13_dac : 3;
uint32_t touch_pad12_dac : 3;
uint32_t touch_pad11_dac : 3;
uint32_t touch_pad10_dac : 3;
};
uint32_t val;
} touch_dac1;
union {
struct {
uint32_t reserved0 : 31;
uint32_t disable_rtc_cpu : 1;
};
uint32_t val;
} cocpu_disable;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
union {
struct {
uint32_t date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} date;

139
components/soc/esp32s3/include/soc/system_reg.h
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@ -102,71 +102,7 @@ extern "C" {
#define SYSTEM_CPUPERIOD_SEL_V 0x3
#define SYSTEM_CPUPERIOD_SEL_S 0
#define SYSTEM_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x14)
/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S))
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0
#define SYSTEM_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x18)
/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S))
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0
#define SYSTEM_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x1C)
/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S))
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0
#define SYSTEM_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x20)
/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S))
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0
#define SYSTEM_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x24)
/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S))
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0
#define SYSTEM_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x28)
/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S))
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0
#define SYSTEM_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x2C)
/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S))
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0
#define SYSTEM_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x30)
/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S))
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF
#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0
#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x34)
#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x14)
/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0))
@ -174,7 +110,7 @@ extern "C" {
#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1
#define SYSTEM_LSLP_MEM_PD_MASK_S 0
#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x38)
#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x18)
/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
/*description: .*/
#define SYSTEM_SPI4_CLK_EN (BIT(31))
@ -368,7 +304,7 @@ extern "C" {
#define SYSTEM_TIMERS_CLK_EN_V 0x1
#define SYSTEM_TIMERS_CLK_EN_S 0
#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x3C)
#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x1C)
/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_USB_DEVICE_CLK_EN (BIT(10))
@ -436,7 +372,7 @@ extern "C" {
#define SYSTEM_PERI_BACKUP_CLK_EN_V 0x1
#define SYSTEM_PERI_BACKUP_CLK_EN_S 0
#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x40)
#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x20)
/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: .*/
#define SYSTEM_SPI4_RST (BIT(31))
@ -630,7 +566,7 @@ extern "C" {
#define SYSTEM_TIMERS_RST_V 0x1
#define SYSTEM_TIMERS_RST_S 0
#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x44)
#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x24)
/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_USB_DEVICE_RST (BIT(10))
@ -698,7 +634,7 @@ extern "C" {
#define SYSTEM_PERI_BACKUP_RST_V 0x1
#define SYSTEM_PERI_BACKUP_RST_S 0
#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x48)
#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x28)
/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
/*description: .*/
#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF
@ -706,7 +642,7 @@ extern "C" {
#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_NUM_S 0
#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x4C)
#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x2C)
/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_LPCLK_RTC_EN (BIT(28))
@ -750,7 +686,7 @@ extern "C" {
#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_B_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x50)
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x30)
/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0))
@ -758,7 +694,7 @@ extern "C" {
#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x54)
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x34)
/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0))
@ -766,7 +702,7 @@ extern "C" {
#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x58)
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x38)
/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0))
@ -774,7 +710,7 @@ extern "C" {
#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x5C)
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x3C)
/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0))
@ -782,7 +718,7 @@ extern "C" {
#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0
#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x60)
#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x40)
/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2))
@ -802,7 +738,7 @@ extern "C" {
#define SYSTEM_RSA_MEM_PD_V 0x1
#define SYSTEM_RSA_MEM_PD_S 0
#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x64)
#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x44)
/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_EDMA_RESET (BIT(1))
@ -816,7 +752,7 @@ extern "C" {
#define SYSTEM_EDMA_CLK_ON_V 0x1
#define SYSTEM_EDMA_CLK_ON_S 0
#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x68)
#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x48)
/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_DCACHE_RESET (BIT(3))
@ -842,7 +778,7 @@ extern "C" {
#define SYSTEM_ICACHE_CLK_ON_V 0x1
#define SYSTEM_ICACHE_CLK_ON_S 0
#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x6C)
#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x4C)
/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
@ -868,7 +804,7 @@ extern "C" {
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x70)
#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x50)
/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31))
@ -894,7 +830,7 @@ extern "C" {
#define SYSTEM_RTC_MEM_CRC_START_V 0x1
#define SYSTEM_RTC_MEM_CRC_START_S 8
#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x74)
#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x54)
/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF
@ -902,7 +838,7 @@ extern "C" {
#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF
#define SYSTEM_RTC_MEM_CRC_RES_S 0
#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x78)
#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x58)
/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1))
@ -916,7 +852,7 @@ extern "C" {
#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1
#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0
#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x7C)
#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x5C)
/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_CLK_EN (BIT(0))
@ -924,7 +860,7 @@ extern "C" {
#define SYSTEM_CLK_EN_V 0x1
#define SYSTEM_CLK_EN_S 0
#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x80)
#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x60)
/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
/*description: .*/
#define SYSTEM_CLK_DIV_EN (BIT(19))
@ -950,7 +886,7 @@ extern "C" {
#define SYSTEM_PRE_DIV_CNT_V 0x3FF
#define SYSTEM_PRE_DIV_CNT_S 0
#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x84)
#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x64)
/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
/*description: .*/
#define SYSTEM_MEM_VT_SEL 0x00000003
@ -982,7 +918,7 @@ extern "C" {
#define SYSTEM_MEM_PATH_LEN_V 0xF
#define SYSTEM_MEM_PATH_LEN_S 0
#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x88)
#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68)
/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6))
@ -1002,7 +938,7 @@ extern "C" {
#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F
#define SYSTEM_COMB_PATH_LEN_LVT_S 0
#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x8C)
#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x6C)
/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6))
@ -1022,7 +958,7 @@ extern "C" {
#define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F
#define SYSTEM_COMB_PATH_LEN_NVT_S 0
#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x90)
#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x70)
/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6))
@ -1042,7 +978,7 @@ extern "C" {
#define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F
#define SYSTEM_COMB_PATH_LEN_HVT_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x94)
#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF
@ -1050,7 +986,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x98)
#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x78)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF
@ -1058,7 +994,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x9C)
#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x7C)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF
@ -1066,7 +1002,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA0)
#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF
@ -1074,7 +1010,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA4)
#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x84)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF
@ -1082,7 +1018,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA8)
#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x88)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF
@ -1090,7 +1026,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xAC)
#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8C)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF
@ -1098,7 +1034,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xB0)
#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x90)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF
@ -1106,7 +1042,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xB4)
#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x94)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF
@ -1114,7 +1050,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xB8)
#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF
@ -1122,7 +1058,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xBC)
#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x9C)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF
@ -1130,7 +1066,7 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xC0)
#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xA0)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: .*/
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF
@ -1139,13 +1075,14 @@ extern "C" {
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0
#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC)
/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012230 ; */
/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101220 ; */
/*description: .*/
#define SYSTEM_DATE 0x0FFFFFFF
#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
#define SYSTEM_DATE_V 0xFFFFFFF
#define SYSTEM_DATE_S 0
#ifdef __cplusplus
}
#endif

16
components/soc/esp32s3/include/soc/system_struct.h
Wyświetl plik

@ -59,14 +59,6 @@ typedef volatile struct {
};
uint32_t val;
} cpu_per_conf;
uint32_t jtag_ctrl_0;
uint32_t jtag_ctrl_1;
uint32_t jtag_ctrl_2;
uint32_t jtag_ctrl_3;
uint32_t jtag_ctrl_4;
uint32_t jtag_ctrl_5;
uint32_t jtag_ctrl_6;
uint32_t jtag_ctrl_7;
union {
struct {
uint32_t lslp_mem_pd_mask : 1;
@ -428,6 +420,14 @@ typedef volatile struct {
};
uint32_t val;
} comb_pvt_err_hvt_site3;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;