kopia lustrzana https://github.com/espressif/esp-idf
spi_flash: Use per-chip flash_ops files for legacy API
Looks like when ESP32-S2 Beta support was merged, the separate files were dropped by accident.pull/5222/head
rodzic
95bc186846
commit
dbdce93d23
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@ -15,6 +15,7 @@ else()
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"cache_utils.c"
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"flash_mmap.c"
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"flash_ops.c"
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"${IDF_TARGET}/flash_ops_${IDF_TARGET}.c"
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)
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set(srcs
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"partition.c")
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@ -36,6 +36,10 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
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{
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const uint8_t *ssrc = (const uint8_t *)src;
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esp_rom_spiflash_result_t rc;
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assert((dest_addr % 16) == 0);
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assert((size % 16) == 0);
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rc = esp_rom_spiflash_unlock();
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if (rc != ESP_ROM_SPIFLASH_RESULT_OK) {
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return rc;
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@ -28,6 +28,9 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
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const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
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esp_rom_spiflash_result_t rc;
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assert((dest_addr % 16) == 0);
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assert((size % 16) == 0);
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if (!esp_ptr_internal(src)) {
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uint8_t block[128]; // Need to buffer in RAM as we write
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while (size > 0) {
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@ -45,6 +45,7 @@
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#include "esp_flash.h"
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#include "esp_attr.h"
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esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size);
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/* bytes erased by SPIEraseBlock() ROM function */
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#define BLOCK_ERASE_SIZE 65536
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@ -434,58 +435,6 @@ out:
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#endif // CONFIG_SPI_FLASH_USE_LEGACY_IMPL
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static IRAM_ATTR esp_err_t spi_flash_write_encrypted_in_rows(size_t dest_addr, const uint8_t *src, size_t size)
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{
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assert((dest_addr % 16) == 0);
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assert((size % 16) == 0);
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/* esp_rom_spiflash_write_encrypted encrypts data in RAM as it writes,
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so copy to a temporary buffer - 32 bytes at a time.
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Each call to esp_rom_spiflash_write_encrypted takes a 32 byte "row" of
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data to encrypt, and each row is two 16 byte AES blocks
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that share a key (as derived from flash address).
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*/
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esp_rom_spiflash_result_t rc = ESP_ROM_SPIFLASH_RESULT_OK;
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WORD_ALIGNED_ATTR uint8_t encrypt_buf[32];
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uint32_t row_size;
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for (size_t i = 0; i < size; i += row_size) {
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uint32_t row_addr = dest_addr + i;
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if (i == 0 && (row_addr % 32) != 0) {
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/* writing to second block of a 32 byte row */
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row_size = 16;
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row_addr -= 16;
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/* copy to second block in buffer */
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memcpy(encrypt_buf + 16, src + i, 16);
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/* decrypt the first block from flash, will reencrypt to same bytes */
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spi_flash_read_encrypted(row_addr, encrypt_buf, 16);
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} else if (size - i == 16) {
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/* 16 bytes left, is first block of a 32 byte row */
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row_size = 16;
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/* copy to first block in buffer */
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memcpy(encrypt_buf, src + i, 16);
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/* decrypt the second block from flash, will reencrypt to same bytes */
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spi_flash_read_encrypted(row_addr + 16, encrypt_buf + 16, 16);
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} else {
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/* Writing a full 32 byte row (2 blocks) */
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row_size = 32;
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memcpy(encrypt_buf, src + i, 32);
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}
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spi_flash_guard_start();
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rc = esp_rom_spiflash_write_encrypted(row_addr, (uint32_t *)encrypt_buf, 32);
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spi_flash_guard_end();
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if (rc != ESP_ROM_SPIFLASH_RESULT_OK) {
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break;
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}
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}
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bzero(encrypt_buf, sizeof(encrypt_buf));
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size)
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{
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esp_err_t err = ESP_OK;
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@ -505,7 +454,7 @@ esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src,
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}
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#ifndef CONFIG_SPI_FLASH_VERIFY_WRITE
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err = spi_flash_write_encrypted_in_rows(dest_addr, (const uint8_t*)src, size);
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err = spi_flash_write_encrypted_chip(dest_addr, src, size);
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COUNTER_ADD_BYTES(write, size);
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spi_flash_guard_start();
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spi_flash_check_and_flush_cache(dest_addr, size);
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@ -535,7 +484,7 @@ esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src,
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}
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#endif
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err = spi_flash_write_encrypted_in_rows(dest_addr + i, src + i, read_len);
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err = spi_flash_write_encrypted_chip(dest_addr + i, src + i, read_len);
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if (err != ESP_OK) {
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break;
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}
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@ -795,78 +744,6 @@ void spi_flash_dump_counters(void)
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#endif //CONFIG_SPI_FLASH_ENABLE_COUNTERS
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#if CONFIG_IDF_TARGET_ESP32S2
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#define SPICACHE SPIMEM0
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#define SPIFLASH SPIMEM1
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#define FLASH_WRAP_CMD 0x77
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esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode)
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{
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uint32_t reg_bkp_ctrl = SPIFLASH.ctrl.val;
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uint32_t reg_bkp_usr = SPIFLASH.user.val;
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SPIFLASH.user.fwrite_dio = 0;
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SPIFLASH.user.fwrite_dual = 0;
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SPIFLASH.user.fwrite_qio = 1;
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SPIFLASH.user.fwrite_quad = 0;
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SPIFLASH.ctrl.fcmd_dual = 0;
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SPIFLASH.ctrl.fcmd_quad = 0;
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SPIFLASH.user.usr_dummy = 0;
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SPIFLASH.user.usr_addr = 1;
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SPIFLASH.user.usr_command = 1;
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SPIFLASH.user2.usr_command_bitlen = 7;
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SPIFLASH.user2.usr_command_value = FLASH_WRAP_CMD;
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SPIFLASH.user1.usr_addr_bitlen = 23;
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SPIFLASH.addr = 0;
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SPIFLASH.user.usr_miso = 0;
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SPIFLASH.user.usr_mosi = 1;
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SPIFLASH.mosi_dlen.usr_mosi_bit_len = 7;
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SPIFLASH.data_buf[0] = (uint32_t) mode << 4;;
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SPIFLASH.cmd.usr = 1;
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while(SPIFLASH.cmd.usr != 0)
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{ }
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SPIFLASH.ctrl.val = reg_bkp_ctrl;
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SPIFLASH.user.val = reg_bkp_usr;
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return ESP_OK;
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}
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esp_err_t spi_flash_enable_wrap(uint32_t wrap_size)
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{
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switch(wrap_size) {
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case 8:
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return spi_flash_wrap_set(FLASH_WRAP_MODE_8B);
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case 16:
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return spi_flash_wrap_set(FLASH_WRAP_MODE_16B);
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case 32:
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return spi_flash_wrap_set(FLASH_WRAP_MODE_32B);
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case 64:
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return spi_flash_wrap_set(FLASH_WRAP_MODE_64B);
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default:
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return ESP_FAIL;
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}
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}
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void spi_flash_disable_wrap(void)
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{
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spi_flash_wrap_set(FLASH_WRAP_MODE_DISABLE);
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}
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bool spi_flash_support_wrap_size(uint32_t wrap_size)
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{
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if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO) || !REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FASTRD_MODE)){
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return ESP_FAIL;
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}
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switch(wrap_size) {
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case 0:
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case 8:
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case 16:
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case 32:
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case 64:
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return true;
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default:
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return false;
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}
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}
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#endif
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#if defined(CONFIG_SPI_FLASH_USE_LEGACY_IMPL) && defined(CONFIG_IDF_TARGET_ESP32S2)
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// TODO esp32s2: Remove once ESP32S2 has new SPI Flash API support
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esp_flash_t *esp_flash_default_chip = NULL;
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