kopia lustrzana https://github.com/espressif/esp-idf
spi: fix issue with closing DMA before CPU reset
rodzic
aa93347972
commit
da9649df53
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@ -116,7 +116,7 @@ void IRAM_ATTR esp_restart_noos(void)
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// Reset timer/spi/uart
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
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//UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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// Set CPU back to XTAL source, no PLL, same as hard reset
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@ -95,7 +95,7 @@ void IRAM_ATTR esp_restart_noos(void)
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// Reset timer/spi/uart
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST);
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | DPORT_UART_RST);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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// Set CPU back to XTAL source, no PLL, same as hard reset
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