kopia lustrzana https://github.com/espressif/esp-idf
gpio: remove legacy rtc_io description for esp32
morris
rodzic
3b371d2d64
commit
d8f2eaf94e
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@ -156,20 +156,6 @@ menu "Driver configurations"
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endmenu # UART Configuration
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menu "RTCIO configuration"
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visible if IDF_TARGET_ESP32
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config RTCIO_SUPPORT_RTC_GPIO_DESC
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bool "Support array `rtc_gpio_desc` for ESP32"
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depends on IDF_TARGET_ESP32
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default n
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help
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The the array `rtc_gpio_desc` will don't compile by default.
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If this option is selected, the array `rtc_gpio_desc` can be compile.
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If user use this array, please enable this configuration.
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endmenu # RTCIO Configuration
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menu "GPIO Configuration"
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visible if IDF_TARGET_ESP32
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@ -1,16 +1,8 @@
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// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/rtc_io_periph.h"
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@ -79,50 +71,3 @@ const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = {
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{RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, 0, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_CHANNEL_16_GPIO_NUM},//14
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{RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, 0, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_CHANNEL_17_GPIO_NUM},//27
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};
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#ifdef CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC
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//Reg,Mux,Fun,IE,Up,Down,Rtc_number
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const rtc_gpio_desc_t rtc_gpio_desc[SOC_GPIO_PIN_COUNT] = {
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{RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_HOLD_M, RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_GPIO0_CHANNEL}, //0
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //1
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{RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_HOLD_M, RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_GPIO2_CHANNEL}, //2
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //3
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{RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_HOLD_M, RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_GPIO4_CHANNEL}, //4
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //5
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //6
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //7
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //8
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //9
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //10
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //11
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{RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_HOLD_M, RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_GPIO12_CHANNEL}, //12
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{RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_HOLD_M, RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_GPIO13_CHANNEL}, //13
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{RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_GPIO14_CHANNEL}, //14
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{RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_HOLD_M, RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_GPIO15_CHANNEL}, //15
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //16
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //17
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //18
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //19
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //20
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //21
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //22
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //23
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //24
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{RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_GPIO25_CHANNEL}, //25
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{RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_HOLD_M, RTC_CNTL_PDAC2_HOLD_FORCE_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_GPIO26_CHANNEL}, //26
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{RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_GPIO27_CHANNEL}, //27
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //28
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //29
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //30
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //31
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{RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_HOLD_M, RTC_CNTL_X32P_HOLD_FORCE_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_GPIO32_CHANNEL}, //32
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{RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_HOLD_M, RTC_CNTL_X32N_HOLD_FORCE_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_GPIO33_CHANNEL}, //33
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{RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, RTC_IO_ADC1_SLP_SEL_M, RTC_IO_ADC1_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO34_CHANNEL}, //34
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{RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, RTC_IO_ADC2_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO35_CHANNEL}, //35
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{RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO36_CHANNEL}, //36
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{RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, RTC_IO_SENSE2_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO37_CHANNEL}, //37
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{RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, RTC_IO_SENSE3_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, RTCIO_GPIO38_CHANNEL}, //38
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{RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, RTC_IO_SENSE4_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, RTCIO_GPIO39_CHANNEL}, //39
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};
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#endif //CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC
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@ -1,19 +1,12 @@
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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//include soc related (generated) definitions
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#include "soc/soc_caps.h"
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@ -79,40 +72,6 @@ extern const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT];
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*/
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extern const int rtc_io_num_map[SOC_GPIO_PIN_COUNT];
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#ifdef CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC
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/**
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* @brief Pin function information for a single GPIO pad's RTC functions.
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*
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* This is an internal function of the driver, and is not usually useful
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* for external use.
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*/
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typedef struct {
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uint32_t reg; /*!< Register of RTC pad, or 0 if not an RTC GPIO */
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uint32_t mux; /*!< Bit mask for selecting digital pad or RTC pad */
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uint32_t func; /*!< Shift of pad function (FUN_SEL) field */
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uint32_t ie; /*!< Mask of input enable */
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uint32_t pullup; /*!< Mask of pullup enable */
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uint32_t pulldown; /*!< Mask of pulldown enable */
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uint32_t slpsel; /*!< If slpsel bit is set, slpie will be used as pad input enabled signal in sleep mode */
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uint32_t slpie; /*!< Mask of input enable in sleep mode */
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uint32_t hold; /*!< Mask of hold enable */
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uint32_t hold_force;/*!< Mask of hold_force bit for RTC IO in RTC_CNTL_HOLD_FORCE_REG */
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uint32_t drv_v; /*!< Mask of drive capability */
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uint32_t drv_s; /*!< Offset of drive capability */
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int rtc_num; /*!< RTC IO number, or -1 if not an RTC GPIO */
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} rtc_gpio_desc_t;
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/**
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* @brief Provides access to a constant table of RTC I/O pin
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* function information.
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*
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* This is an internal function of the driver, and is not usually useful
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* for external use.
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*/
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extern const rtc_gpio_desc_t rtc_gpio_desc[SOC_GPIO_PIN_COUNT];
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#endif // CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC
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#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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#ifdef __cplusplus
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@ -21,3 +21,8 @@ ADC
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---
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Previous `driver/adc2_wifi_private.h` has been moved to `esp_private/adc2_wifi.h`.
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GPIO
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----
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The previous Kconfig option `RTCIO_SUPPORT_RTC_GPIO_DESC` has been removed, thus the ``rtc_gpio_desc`` array is unavailable. Please use ``rtc_io_desc`` array instead.
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@ -1652,7 +1652,6 @@ components/soc/esp32/ledc_periph.c
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components/soc/esp32/mcpwm_periph.c
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components/soc/esp32/pcnt_periph.c
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components/soc/esp32/rmt_periph.c
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components/soc/esp32/rtc_io_periph.c
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components/soc/esp32/sdio_slave_periph.c
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components/soc/esp32/sdmmc_periph.c
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components/soc/esp32/sigmadelta_periph.c
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@ -2018,7 +2017,6 @@ components/soc/include/soc/mcpwm_periph.h
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components/soc/include/soc/pcnt_periph.h
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components/soc/include/soc/rmt_periph.h
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components/soc/include/soc/rtc_cntl_periph.h
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components/soc/include/soc/rtc_io_periph.h
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components/soc/include/soc/rtc_periph.h
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components/soc/include/soc/sdio_slave_periph.h
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components/soc/include/soc/sdmmc_periph.h
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